FSCLE, FSC Lock Enable, Address 0x51 [7] The FSC" />
參數(shù)資料
型號: ADV7188BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 34/112頁
文件大?。?/td> 0K
描述: IC DECODER VID MULTIFORM 80LQFP
標準包裝: 1
類型: 視頻解碼器
應用: 機頂盒,視頻播放器,錄音機
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
ADV7188
Rev. A | Page 28 of 112
FSCLE, FSC Lock Enable, Address 0x51 [7]
The FSCLE bit allows the user to choose if the status of the
color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits [1:0] in Status
Register 1. The FSCLE bit must be set to 0 when operating in
YPrPb (component) mode to generate a reliable horizontal lock
status bit (INST_HLOCK).
0 (default)—Makes the overall lock status dependent on the
horizontal sync lock.
1—Makes the overall lock status dependent on the horizontal
sync lock and the FSC lock.
CIL [2:0], Count-Into-Lock, Address 0x51 [2:0]
CIL [2:0] determines the number of consecutive lines the system
must remain in the into-lock condition before reporting a locked
state in Status Register 1 [1:0]. It counts the value in lines of video.
Table 25. CIL [2:0] Function
CIL [2:0]
Description
000
1 line of video
001
2 lines of video
010
5 lines of video
011
10 lines of video
100 (default)
100 lines of video
101
500 lines of video
110
1000 lines of video
111
100,000 lines of video
COL [2:0], Count-Out-of-Lock, Address 0x51 [5:3]
COL [2:0] determines the number of consecutive lines the system
must be in the out-of-lock condition before reporting an unlocked
state in Status Register 0 [1:0]. It counts the value in lines of video.
Table 26. COL [2:0] Function
COL [2:0]
Description
000
1 line of video
001
2 lines of video
010
5 lines of video
011
10 lines of video
100 (default)
100 lines of video
101
500 lines of video
110
1000 lines of video
111
100,000 lines of video
VS_COAST_MODE [1:0], Address 0xF9 [3:2]
These bits are used to set the VS free-run (coast) frequency.
Table 27. VS_COAST_MODE [1:0] Function
VS_COAST_MODE [1:0]
Description
00 (default)
Autocoast mode—follows VS
frequency from last video input
01
Forces 50 Hz coast mode
10
Forces 60 Hz coast mode
11
Reserved
ST_NOISE_VLD, Sync Tip Noise Measurement Valid,
Address 0xDE [3], Read Only
This read-only bit measures whether ST_NOISE is valid or invalid.
0—The ST_NOISE [10:0] measurement is invalid.
1 (default)—The ST_NOISE [10:0] measurement is valid.
ST_NOISE [10:0], Sync Tip Noise Measurement,
Addresses 0xDE [2:0], 0xDF [7:0]
The ST_NOISE [10:0] measures the noise in the horizontal sync
tip over four fields and shows a readback value of the average noise.
ST_NOISE_VLD must be 1 for this measurement to be valid.
One bit of ST_NOISE [10:0] = one ADC code.
One bit of ST_NOISE [10:0] = 1.6 V/4096 = 390.625 μV.
COLOR CONTROLS
These registers allow the user to control the appearance of the
picture, including control of the active data in the event of video
being lost. These controls are independent of any other control.
For instance, brightness control is independent of picture clamping,
although both controls affect the dc level of the signal.
CON [7:0], Contrast Adjust, Address 0x08 [7:0]
These bits allow the user to adjust the contrast of the picture.
Table 28. CON [7:0] Function
CON [7:0]
Description
0x80 (default)
Gain on luma channel = 1
0x00
Gain on luma channel = 0
0xFF
Gain on luma channel = 2
SD_SAT_CB [7:0], SD Saturation Cb Channel,
Address 0xE3 [7:0]
These bits allow the user to control only the gain of the Cb
channel. The user can adjust the saturation of the picture.
Table 29. SD_SAT_CB [7:0] Function
SD_SAT_CB [7:0]
Description
0x80 (default)
Gain on Cb channel = 1
0x00
Gain on Cb channel = 0
0xFF
Gain on Cb channel = 2
SD_SAT_CR [7:0], SD Saturation Cr Channel,
Address 0xE4 [7:0]
These bits allow the user to control only the gain of the Cr
channel. The user can adjust the saturation of the picture.
Table 30. SD_SAT_CR [7:0] Function
SD_SAT_CR [7:0]
Description
0x80 (default)
Gain on Cr channel = 1
0x00
Gain on Cr channel = 0
0xFF
Gain on Cr channel = 2
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