- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1901 > ADV7188BSTZ (Analog Devices Inc)IC DECODER VID MULTIFORM 80LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADV7188BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 26/112頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DECODER VID MULTIFORM 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 視頻解碼器 |
| 應(yīng)用： | 機(jī)頂盒，視頻播放器，錄音機(jī) |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)
ADV7188
Rev. A | Page 20 of 112
FB_INV, Address 0xED [3], Write Only
The interpretation of the polarity of the signal applied to the FB
pin can be changed using FB_INV.
0 (default)—The fast blank pin is active high.
1—The fast blank pin is active low.
Readback of FB Pin Status
FB_STATUS [3:0], Address 0xED [7:4]
FB_STATUS [3:0] is a readback value that provides the system
information on the status of the FB pins, as shown in Table 16.
FB Timing
FB_SP_ADJUST [3:0], Address 0xEF [7:4]
The critical information extracted from the FB signal is the time
at which it switches relative to the input video. Due to small
timing inequalities either on the IC or on the PCB, it may be
necessary to adjust the result by a fraction of one clock cycle.
This is controlled by FB_SP_ADJUST [3:0].
Each LSB of FB_SP_ADJUST [3:0] corresponds to th of an ADC
clock cycle. Increasing the value is equivalent to adding delay to
the FB signal. The reset value is chosen to produce equalized
channels when the ADV7188 internal antialiasing filters are
enabled and there are only intentional delays on the PCB.
The default value of FB_SP_ADJUST [3:0] is 0100.
Alignment of FB Signal
FB_DELAY [3:0], Address 0xF0 [3:0]
In the event of misalignment between the FB input signal and
the other input signals (CVBS and RGB) or unequalized delays
in their processing, it is possible to alter the delay of the FB
signal in 28.63636 MHz clock cycles. (For a finer granularity
delay of the FB signal, refer to the FB_SP_ADJUST [3:0],
The default value of FB_DELAY [3:0] is 0100.
Color Space Converter Manual Adjust
FB_CSC_MAN, Address 0xEE [7]
As shown in Figure 9, the data from the CVBS and RGB sources
are converted to YPbPr before being combined. For the RGB
source, CSC must be used to perform this conversion. When
SCART support is enabled, the parameters for CSC are
automatically configured for this operation.
If the user wishes to use a different conversion matrix, this
autoconfiguration can be disabled and the CSC can be manually
programmed. For details on this manual configuration, contact an
Analog Devices representative.
0 (default)—The CSC is configured automatically for the RGB-
to-YPrPb conversion.
1—The CSC can be configured manually (not recommended).
Table 16. FB_STATUS Functions
FB_STATUS [3:0]
Bit Name
Description
0
FB_STATUS.0
FB_RISE. A high value indicates that there has been a rising edge on FB since the last
I2C read. The value is cleared by an I2C read (this is a self-clearing bit).
1
FB_STATUS.1
FB_FALL. A high value indicates that there has been a falling edge on FB since the last
I2C read. The value is cleared by an I2C read (this is a self-clearing bit).
2
FB_STATUS.2
FB_STAT. The value of the FB input pin at the time of the read.
3
FB_STATUS.3
FB_HIGH. A high value indicates that there has been a rising edge on FB since the last
I2C read. The value is cleared by an I2C read (this is a self-clearing bit).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7189BBSTZ | IC VIDEO DECODER SDTV 80-LQFP |
| ADV7194KSTZ | IC ENCODER VIDEO EXT-10 80-LQFP |
| ADV7202KSTZ | IC CODEC VIDEO 10BIT 64LQFP |
| ADV7311KST | IC VID ENC 6-12BIT DAC'S 64LQFP |
| ADV7321KSTZ | IC VID ENC 6-12BIT DAC'S 64LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7189 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189B | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ | 功能描述:IC VIDEO DECODER SDTV 80-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7189BBSTZ268H | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BBSTZ268H2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。