Bit1 Address Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes Re" />
參數(shù)資料
型號: ADV7188BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 105/112頁
文件大小: 0K
描述: IC DECODER VID MULTIFORM 80LQFP
標(biāo)準(zhǔn)包裝: 1
類型: 視頻解碼器
應(yīng)用: 機(jī)頂盒,視頻播放器,錄音機(jī)
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
ADV7188
Rev. A | Page 92 of 112
Bit1
Address
Register
Bit Description
7 6 5 4 3 2 1 0 Comments
Notes
Reserved.
0 0 0 0 0 1 Set to default
0
SFL compatible with ADV717x and
ADV73xx encoders
SFL_INV. This bit controls the behavior of the
PAL switch bit.
1
SFL compatible with ADV7190/
ADV7191/ADV7194 encoders
0x41
Resample Control
Reserved.
0
Set to default
0x48
Gemstar Control 1
GDECEL [15:8]. See the Comments column.
0 0 0 0 0 0 0 0
0x49
Gemstar Control 2
GDECEL [7:0]. See the Comments column.
0 0 0 0 0 0 0 0
GDECEL [15:0]. The 16 individual
enable bits that select the lines of
video (even field Lines 10 to 25)
that the decoder checks for
Gemstar-compatible data.
LSB = Line 10; MSB = Line 25.
Default = do not check for Gemstar-
compatible data on any lines
(Lines 10 to 25) in even fields
0x4A
Gemstar Control 3
GDECOL [15:8]. See the Comments column.
0 0 0 0 0 0 0 0
0x4B
Gemstar Control 4
GDECOL [7:0]. See the Comments column.
0 0 0 0 0 0 0 0
GDECOL [15:0]. The 16 individual
enable bits that select the lines of
video (odd field Lines 10 to 25)
that the decoder checks for
Gemstar-compatible data.
LSB = Line 10; MSB = Line 25.
Default = do not check for Gemstar-
compatible data on any lines
(Lines 10 to 25) in odd fields.
0 Split data into half byte
To avoid 0x00 and 0xFF codes.
GDECAD. This bit controls the manner in
which decoded Gemstar data is inserted into
the horizontal blanking period.
1 Output in straight 8-bit format
0x4C
Gemstar Control 5
Reserved.
x x x x
0 0 0
Undefined
0x4D
CTI DNR Control 1
0 Disable CTI
CTI_EN. CTI enable.
1 Enable CTI
0
Disable CTI alpha blender
CTI_AB_EN. CTI alpha blend enable. This bit
enables the mixing of the transient improved
chroma with the original signal.
1
Enable CTI alpha blender
0 0
Sharpest mixing
0 1
Sharp mixing
1 0
Smooth mixing
CTI_AB [1:0]. CTI alpha blend control. These
bits control the behavior of the alpha-blend
circuitry.
1 1
Smoothest mixing
Reserved.
0
Set to default
0
Bypass the DNR block
DNR_EN. This bit enables or bypasses the
DNR block.
1
Enable the DNR block
Reserved.
1 1
Set to default
0x4E
CTI DNR Control 2
CTI_C_TH [7:0]. CTI chroma threshold. These
bits specify how big the amplitude step must
be to be steepened by the CTI block.
0 0 0 0 1 0 0 0
0x50
CTI DNR Control 4
DNR_TH [7:0]. DNR threshold. These bits
specify the maximum edge that is interpreted
as noise and is therefore blanked.
0 0 0 0 1 0 0 0 Set to 0x04 for A/V input; set to
0x0A for tuner input
0 0 0 1 line of video
0 0 1 2 lines of video
0 1 0 5 lines of video
0 1 1 10 lines of video
1 0 0 100 lines of video
1 0 1 500 lines of video
1 1 0 1000 lines of video
CIL [2:0]. Count-into-lock. These bits determine
the number of lines the system must remain
in lock before reporting a locked status.
1 1 1 100,000 lines of video
0 0 0
1 line of video
0 0 1
2 lines of video
0 1 0
5 lines of video
0 1 1
10 lines of video
1 0 0
100 lines of video
1 0 1
500 lines of video
1 1 0
1000 lines of video
COL [2:0]. Count-out-of-lock. These bits
determine the number of lines the system
must remain out-of-lock before reporting
an unlocked status
1 1 1
100,000 lines of video
0
Over field with vertical information
SRLS. Select raw lock signal. Selects the
source for determining the lock status.
1
Line-to-line evaluation
0
Lock status set only by
horizontal lock
0x51
Lock Count
FSCLE. FSC lock enable.
1
Lock status set by horizontal lock
and subcarrier lock.
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