參數(shù)資料
型號: ADV7188BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 33/112頁
文件大小: 0K
描述: IC DECODER VID MULTIFORM 80LQFP
標準包裝: 1
類型: 視頻解碼器
應用: 機頂盒,視頻播放器,錄音機
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-LQFP(14x14)
包裝: 托盤
ADV7188
Rev. A | Page 27 of 112
Lock-Related Controls
Lock information is presented to the user through Bits [1:0] of
Status Register 1. See the Status Register 1 [7:0], Address 0x10
[7:0] section. Figure 13 outlines the signal flow and the controls
that are available to influence how the lock status information is
generated.
SRLS, Select Raw Lock Signal, Address 0x51 [6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status, which is indicated via Status Register 1,
Bits [1:0].
The TIME_WIN signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming video. It
reacts quickly.
The FREE_RUN signal evaluates the properties of the incoming
video over several fields, taking vertical synchronization
information into account.
0 (default)—Selects the FREE_RUN signal.
1—Selects the TIME_WIN signal.
054
78
-0
13
1
0
TIME_WIN
FREE_RUN
IN_LOCK
SELECT THE RAW LOCK SIGNAL
SRLS
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TAKE FSC LOCK INTO ACCOUNT
FSCLE
LOST_LOCK
FSC LOCK
1
0
COUNTER INTO LOCK
COUNTER OUT OF LOCK
MEMORY
Figure 13. Lock-Related Signal Path
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