參數(shù)資料
型號(hào)： ADV7188BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 12/112頁
文件大?。?/td> 0K
描述： IC DECODER VID MULTIFORM 80LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 機(jī)頂盒，視頻播放器，錄音機(jī)
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
ADV7188
Rev. A | Page 109 of 112
PCB LAYOUT RECOMMENDATIONS
The ADV7188 is a high precision, high speed mixed-signal
device. To achieve the maximum performance from the part, it
is important to have a well laid out PCB board. The following is
a guide for designing a board using the ADV7188.
ANALOG INTERFACE INPUTS
Care should be taken when routing the inputs on the PCB.
Track lengths should be kept to a minimum, and 75 Ω trace
impedances should be used when possible. Trace impedances
other than 75 Ω increase the chance of reflections.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with
0.1 μF and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin.
Also, avoid placing the capacitor on the side of the PC board
opposite from the ADV7188, because doing so interposes
resistive vias in the path. The decoupling capacitors should be
located between the power plane and the power pin. Current
should flow from the power plane to the capacitor to the power
pin. Do not make the power connection between the capacitor
and the power pin. Placing a via underneath the 100 nF capacitor
pads, down to the power plane, is generally the best approach
(see Figure 49).
054
78-
051
VDD
GND
10nF
100nF
VIA TO SUPPLY
VIA TO GND
Figure 49. Recommended Power Supply Decoupling
It is particularly important to maintain low noise and good
stability of PVDD. Careful attention must be paid to regulation,
filtering, and decoupling. It is highly desirable to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD, DVDD, DVDDIO, and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can, in turn, produce changes in the regulated
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PVDD, from a different, cleaner power
source, for example, from a 12 V supply.
It is also recommended to use a single ground plane for the
entire board. This ground plane should have a space between
the analog and digital sections of the PCB (see Figure 50).
05
478
-05
2
ANALOG
SECTION
DIGITAL
SECTION
ADV7188
Figure 50. PCB Ground Layout
Experience has repeatedly shown that the noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to place a single ground plane
under the ADV7188. The location of the split should be under the
ADV7188. For this case, it is even more important to place
components wisely because the current loops are much longer
(current takes the path of least resistance). An example of a current
loop is from the power plane to ADV7188 to digital output trace to
digital data receiver to digital ground plane to analog ground plane.
PLL
Place the PLL loop filter components as close as possible to the
ELPF pin. Do not place any digital or other high frequency
traces near these components. Use the values suggested in
Figure 52 with tolerances of 10% or less.
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs drive.
Longer traces have higher capacitance, which requires more
current, causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7188.
If series resistors are used, place them as close as possible to the
ADV7188 pins. However, try not to add vias or extra length to
the output trace to make the resistors closer.
If possible, limit the capacitance that each digital output drives
to less than 15 pF. This can easily be accomplished by keeping
traces short and by connecting the outputs to only one device.
Loading the outputs with excessive capacitance increases the
current transients inside the ADV7188, creating more digital
noise on its power supplies.
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ADV7189BBSTZ268H 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder
ADV7189BBSTZ268H2 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder
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