參數(shù)資料
型號(hào)： AD9852ASQ
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： CMOS 300 MHz Complete-DDS
中文描述： PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80
封裝： MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 6/42頁(yè)
文件大?。?/td> 424K
代理商： AD9852ASQ
AD9852
–6–
REV. 0
Pin
No.
55
Pin Name
DACBP
Function
Common Bypass Capacitor Connection for Both DACs. A 0.01
μ
F chip cap from this pin to AVDD
improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR degradation).
Common Connection for Both DACs to Set the Full-Scale Output Current. R
SET
= 39.9/I
OUT
.
Normal R
SET
range
is from 8 k
(5 mA) to 2 k
(20 mA).
This pin provides the connection for the external zero compensation network of the REFCLK
Multiplier’s PLL loop filter. The zero compensation network consists of a 1.3 k
resistor in series
with a 0.01
μ
F capacitor. The other side of the network should be connected to AVDD as close as
possible to Pin 60. For optimum phase noise performance, the REFCLK Multiplier can be bypassed
by setting the “Bypass PLL” bit in control register 1E.
Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and REFCLKB ENABLE (Pins 69 and 68 respectively). The minimum differential signal amplitude
required is 800 mV p-p. The centerpoint or common-mode range of the differential signal ranges
from 1.6 V to 1.9 V.
The Complementary (180 Degrees Out-of-Phase) Differential Clock Signal. User should tie this pin
high or low when single-ended clock mode is selected. Same signal levels as REFCLK.
Single-Ended Reference Clock Input or One of Two Differential Clock Signals. Normal 3.3 V CMOS
logic levels or 1 V p-p sine wave centered about 1.6 V.
Selects Between Serial Programming Mode (Logic LOW) and Parallel Programming Mode
(Logic High).
Initializes the serial/parallel programming bus to prepare for user programming; sets programming
registers to a “do-nothing” state defined by the default values seen in the Table V. Active on logic
high. Asserting MASTER RESET is essential for proper operation upon power-up.
56
DAC R
SET
61
PLL FILTER
64
DIFF CLK
68
REFCLKB
69
REFCLK
70
S/P SELECT
71
MASTER
RESET
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9852ASQZ 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP
AD9852AST 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ C-DDS SYNTHESIZER - Bulk 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER
AD9852ASTZ 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9852ASTZ 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80
AD9852ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
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