參數(shù)資料
型號(hào)： AD9852ASQ
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： CMOS 300 MHz Complete-DDS
中文描述： PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80
封裝： MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 24/42頁(yè)
文件大?。?/td> 424K
代理商： AD9852ASQ
AD9852
–24–
REV. 0
Data in the I/O Port Buffers is stored until overwritten by changes
in program instructions supplied by the user or until power is
removed. An I/O Update clocks-in the data from the I/O Buffers
to the DDS Programming Registers where it is executed.
AM
—amplitude modulation of the sine DACs is possible using
the I/O port to control 12-bit digital multiplier stages that precede
the DACs. The multipliers can also be used to set the DAC
outputs between zero- and full-scale for static amplitude adjust-
ment. See the “Shaped On/Off Keying” description for more
information. Shaped keying function does not apply to the
Control DAC.
High-Speed Comparator
—optimized for high speed, >300 MHz
toggle rate, low jitter, sensitive input, built-in hysteresis and
an output level of 1 V p-p minimum into 50
or CMOS logic
levels into high impedance loads. The comparator can be sepa-
rately powered down to conserve power. This comparator is
used in “clock generator” applications to square up a bandpass
or low-pass filtered sine wave.
Eight-Bit Ramp Rate Clock
—when Shaped On/Off Keying is
engaged, this down-counter takes the system clock (300 MHz
maximum), and divides it by an 8-bit binary value (programmed
by the user) to produce a user-defined clock. The clock outputs
one pulse every time the counter counts down to zero. This clock is
used to set the rate-of-change of the 12-bit digital multipliers of
the I and Q DACs to perform an output shaping function.
Twenty-Bit Ramp Rate Clock
—when selected, this down-
counter takes the system clock (300 MHz maximum) and
divides it by a 20-bit binary value (programmed by the user) to
produce a user-defined clock. The clock outputs one pulse every
time the counter counts down to zero. This clock is used to
set the rate-of-frequency-change of the ramped FSK or FM
Chirp modes.
Forty-Eight-Bit Delta Frequency Register
—is used only in
the Chirp and ramped-FSK modes. This register is loaded with a
48-bit word that represents the frequency increment value of
Frequency Accumulator (ACCU 1) whose output will be added
to a frequency that is set in either F1 or F2 frequency registers.
This register is periodically incremented at a rate set by the
20-bit ramp rate clock (150 MHz maximum).
Forty-Eight-Bit Delta Frequency Register
—is programmed
with a 48-bit Frequency Tuning Word that is input to the 48-bit
Phase Accumulator (ACCU 2) and determines the output fre-
quency of the DDS in the single-tone mode. When ramped-FSK
or Chirp are selected, this register is sent to a digital adder where
it is summed with the output of ACCU 1 before being input
to ACCU 2. Therefore, the signal sent to ACCU 2 may be
either static or changing at a rate of up to 150 million 48-bit
frequency tuning words per second.
Power-Down
—Several individual stages, when not needed,
can be powered down to reduce power consumption via the
programming registers while still maintaining functionality of
desired stages. These stages are identified in the Register Layout
table, address 1D hex. Power-down is achieved by setting the
specified bits to logic high. A logic low indicates that the stages are
powered up.
Furthermore, and perhaps most significantly, two intensely digital
stages, the Inverse Sinc filters and the Digital Multiplier stages,
can be bypassed to achieve significant power reduction through
programming of the control registers in address 20 hex. Again,
logic high will cause the stage to be bypassed. Of particular
importance is the Inverse Sinc filter as this stage consumes a
significant amount of power.
A full power-down occurs when all four
PD
Bits in control
register 1D hex are set to logic high. This reduces power
consumption to approximately 10 mW (3 mA).
Master RESET
—logic high active, must be held high for a
minimum of 10 system clock cycles. This causes the communi-
cations bus to be initialized and loads default values listed in the
Table V.
相關(guān)PDF資料
PDF描述
AD9852AST CMOS 300 MHz Complete-DDS
AD9853-45PCB Programmable Digital OPSK/16-QAM Modulator
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AD9853AS Programmable Digital OPSK/16-QAM Modulator
AD9854ASQ CMOS 300 MHz Quadrature Complete-DDS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9852ASQZ 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP
AD9852AST 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ C-DDS SYNTHESIZER - Bulk 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER
AD9852ASTZ 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9852ASTZ 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80
AD9852ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
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