- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD9852ASQ (ANALOG DEVICES INC) CMOS 300 MHz Complete-DDS PDF資料下載
參數(shù)資料
| 型號： | AD9852ASQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300 MHz Complete-DDS |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80 |
| 封裝： | MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 29/42頁 |
| 文件大?。?/td> | 424K |
| 代理商： | AD9852ASQ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
AD9852
–29–
REV. 0
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
17
16
15
14
13
12
11
10
SDIO
SCLK
CS
IR WRITE PHASE
DATA TRANSFER – TWO-BYTE WRITE
Figure 55. Data Write Cycle, SCLK Idle High
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
17
16
15
14
13
12
11
10
SDIO
SDO
SCLK
CS
IR WRITE PHASE
DATA TRANSFER – TWO-BYTE READ
Figure 56. Data Read Cycle, 3-Wire Configuration, SCLK Idle Low
MSB/LSB TRANSFERS
The AD9852 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 1 of serial register bank 20h.
When this bit is set active high, the AD9852 serial port is in
LSB first format. This bit defaults low, to the MSB first format.
The instruction byte must be written in the format indicated by
Bit 1 of serial register bank 20h. That is, if the AD9852 is in
LSB first mode, the instruction byte must be written from
least significant bit to most significant bit.
Update Clock Operation
Programming the AD9852 is asynchronous to the system clock
with all data being stored in a buffer memory that does not
immediately affect the part operation. The buffer memory is
transferred to the register bank synchronous to system clock.
The register bank information affects part operation.
This transfer of data can occur automatically, with frequency of
updates programmable by the user, or can occur completely under
user control.
Complete user control, referred to as external update mode,
allows the user to drive the I/O UD signal from their ASIC or
DSP. The AD9852 I/O UD pin is configured as an input in
external update mode. A rising edge on I/O UD indicates to
the AD9852 that the contents of the buffer memory is to be
transferred to the register bank. The design uses an edge detector
to signal the AD9852 to transfer data which allows a very small
minimum high pulse width requirement (two system clock peri-
ods). Its important to note that if the user keeps I/O UD high,
the AD9852 will NOT continuously update the register bank.
Internal update mode, in which the AD9852 transfers data from
the buffer memory to the register bank automatically, configures
the AD9852 I/O UD pin as an output. The AD9852 generates a
high pulse on I/O UD pin to signal the user that the buffer memory
has just been transferred to the register bank. The minimum
high pulsewidth is designed to be eight system clock cycles (min).
The I/O UD signal can be used as an interrupt within the system.
Its important to note that as an output I/O UD pin will not have
anything approaching a 50/50 duty cycle for slower update rates.
Programming the Update Clock register for values less than five
will cause the I/O UD pin to remain high. The update clock func-
tionality still works, its just that the user cannot use the signal as
an indication that data is transferring. This is an affect of the
minimum high pulse time when I/O UD is an output.
For internal update clock operation, the rate which the updates
occur is programmed into the update clock register. The update
clock register is 32 bits and the value written into the register
corresponds to HALF the number of clock cycles between updates.
That is, if a value of 00_00_00_0A (hex), is written into the update
clock register the rising edge of the I/O UD pin will occur every
20 cycles (0A hex equals 10 decimal).
CONTROL REGISTER
The Control Register is located in the shaded portion of the
Table V at address 1D through 20 hex. It is composed of 32
bits. Bit 31 is located at the top left position and Bit 0 is located
in the lower right position of the shaded table portion. The reg-
ister has been subdivided below to make it easier to locate the
text associated with specific control categories.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9852AST | CMOS 300 MHz Complete-DDS |
| AD9853-45PCB | Programmable Digital OPSK/16-QAM Modulator |
| AD9853-65PCB | Programmable Digital OPSK/16-QAM Modulator |
| AD9853AS | Programmable Digital OPSK/16-QAM Modulator |
| AD9854ASQ | CMOS 300 MHz Quadrature Complete-DDS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9852ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP |
| AD9852AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ C-DDS SYNTHESIZER - Bulk 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9852ASTZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASTZ | 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80 |
| AD9852ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。