參數(shù)資料
型號： AD9852ASQ
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： CMOS 300 MHz Complete-DDS
中文描述： PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80
封裝： MS-026-BEC, LQFP-80
文件頁數(shù)： 30/42頁
文件大?。?/td> 424K
代理商： AD9852ASQ
AD9852
–30–
REV. 0
Power-Down Functions
Four bits are available to power down the AD9852. Each bit is
active high, that is, they default low and a Logic 1 causes the
power-down function to be working, The four bits all reside in
the same control byte such that one IO write cycle can complete
a full power-down by writing all four bits true simultaneously.
The four bits are located in Control Register [28, 26:24] and
are described below. The default state for these bits is Logic 0,
inactive.
CR[31:29] are open.
CR[28] is the comparator power-down bit. When set (Logic 1),
this signal indicates to the comparator that a power-down mode
is active.
CR[27] must always be written to logic zero. Writing this bit to
Logic 1 causes the AD9852 to stop working until a master reset
is applied.
CR[26] is the Control DAC power-down bit. When set (Logic
1), this signal indicates to the Control DAC that a power-down
mode is active.
CR[25] is the full DAC power-down bit. When set (Logic 1), this
signal indicates to both the cosine and Control DACs, as well as
the reference, that a power-down mode is active.
CR[24] is the digital power-down bit. When set (Logic 1), this
signal indicates to the digital section that a power-down mode is
active. Within the digital section, the clocks will be forced to dc,
effectively powering down the digital section. The REFCLK
input will still be seen by the PLL and the PLL will continue to
output the higher frequency.
REFCLK Multiplier PLL Functions
Seven control register bits, located in the Control Register
[22:16] positions, relate to the PLL.
CR[23] is reserved, write to zero.
CR[22] is the PLL range bit. The PLL range bit controls the
VCO gain. The power-up state of the PLL range bit is Logic 1,
higher gain for frequencies above 200 MHz.
CR[21] is the bypass PLL bit, active high. When active, the PLL is
powered down and the REFCLK input is used to drive the system
clock signal. The power-up state of the bypass PLL bit is Logic 1,
PLL bypassed.
CR[20:16] bits are the PLL multiplier factor. These bits are the
REFCLK multiplication factor unless the bypass PLL bit is set.
The PLL multiplier valid range is from 4 to 20, inclusive.
Other Operational Functions
CR[15] is the clear accumulator 1 bit. This bit has a one-shot
type function. When written active, Logic 1, a clear accumulator
1 signal is sent to the DDS logic, resetting the accumulator value to
zero. The bit is then automatically reset, but the buffer memory
is not reset. This bit allows the user to easily create a sawtooth
frequency sweep pattern with very little (or no) user input
required. This bit is intended for chirp mode only, but there is
no logic to suppress its functionality in other modes.
CR[14] is the clear accumulator bit. This bit, active high, holds
both the accumulator 1 and accumulator 2 values at zero for as
long as the bit is active. This allows the DDS phase to be initial-
ized via the I/O port.
CR[13] is the triangle bit. When this bit is set, the AD9852 will
automatically perform a continuous frequency sweep from the
Frequency 1 to Frequency 2 and back. The effect is a triangular
frequency sweep. When this bit is set, the operating mode must
be set to ramped FSK.
CR[11:9] are the three bits that describe the five operating modes
of the AD9852:
0h = Single-Tone Mode
1h = FSK Mode
2h = Ramped FSK mode
3h = Chirp Mode
4h = PSK Mode
CR[8] is the internal update active bit. When this bit is set to
Logic 1, the I/O UD pin is an output and the AD9852 generates
the I/O UD signal. When Logic 0, external I/O UD functionality
is performed, the I/O UD pin is configured as an input.
CR[7] reserved, write to zero.
CR[6] is the bypass of the inverse sinc filter bit. When set, the
data from the DDS block goes directly to the shaped keying
logic and the clock to the inverse sinc filter is stopped. Default
is clear, filter enabled.
CR[5] is the shaped keying enable bit. When set the output
ramping function is enabled and is performed in accordance with
the CR[4] bit requirements.
CR[4] is the internal/external shaped keying control bit. When set
Logic 1, the shaped keying factor will be internally generated and
applied to the I path. When clear, the shaped keying function is
externally controlled by the user and the shaped keying factor is
the I output shaped keying register values. The two registers
that are the ramp factors also default low such that the output is
off at power-up and until the device is programmed by the user.
CR[3:2] reserved, write to zero.
CR[1] is the serial port MSB/LSB first bit. Defaults low, MSB
first.
CR[0] is the serial port SDO active bit. Defaults low, inactive.
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相關代理商/技術參數(shù)
參數(shù)描述
AD9852ASQZ 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP
AD9852AST 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ C-DDS SYNTHESIZER - Bulk 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER
AD9852ASTZ 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9852ASTZ 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80
AD9852ASTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS
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