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參數(shù)資料
| 型號(hào)： | AD9852ASQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300 MHz Complete-DDS |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80 |
| 封裝： | MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 424K |
| 代理商： | AD9852ASQ |
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AD9852
–26–
REV. 0
Interfacing and Programming the AD9852
The AD9852 Register Layout, shown in Table V, contains the
information that programs the chip for the desired functionality.
While many applications will require very little programming to
configure the AD9852, some will make use of all twelve acces-
sible register banks. The AD9852 supports an 8-bit byte parallel
I/O operation or an SPI-compatible serial I/O operation. All
accessible registers can be written and read back in either
I/O operating mode.
An external pin, S/P SELECT, is used to configure the I/O mode.
Systems that use the parallel I/O mode must connect the S/P
SELECT pin to V
DD
. Systems that operate in the serial I/O mode
must tie the S/P SELECT pin to GND.
Regardless of mode, the I/O port data is written to a buffer
memory that does NOT affect operation of the part until the
contents of the buffer memory are transferred to the register
banks. This transfer of information occurs, synchronously, to the
system clock and occurs in one of two ways:
A<5:0>
D<7:0>
RD
A1
D1
A2
D2
A3
D3
T
RDHOZ
T
RDLOV
T
AHD
T
ADV
SPECIFICATION
T
ADV
T
AHD
T
RDLOV
T
RDHOZ
VALUE
15
5
15
10
DESCRIPTION
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD
LOW TO OUTPUT VALID (MAXIMUM)
RD
HIGH TO DATA THREE-STATE (MAXIMUM)
Figure 49. Parallel Port Read Timing Diagram
D<7:0>
WR
D1
D2
D3
SPECIFICATION
T
ASU
T
DSU
T
ADH
T
DHD
T
WRLOW
T
WRHIGH
T
WR
VALUE
4ns
2ns
5ns
0ns
3ns
7ns
3ns
DESCRIPTION
ADDRESS SETUP TIME TO
WR
SIGNAL ACTIVE
DATA SETUP TIME TO
WR
SIGNAL INACTIVE
ADDRESS HOLD TIME TO
WR
SIGNAL INACTIVE
DATA HOLD TIME TO
WR
SIGNAL INACTIVE
WR
SIGNAL MINIMUM LOW TIME
WR
SIGNAL MINIMUM HIGH TIME
WR
SIGNAL MINIMUM PERIOD
A<5:0>
A1
A2
A3
T
ASU
T
AHD
T
WRHIGH
T
WRLOW
T
DHD
T
DSU
T
WR
Figure 50. Parallel Port Write Timing Diagram
1. Internally, controlled at a rate programmable by the user or,
2. Externally, controlled by the user. I/O operations can occur in
the absence of REFCLK but the data cannot be moved from
the buffer memory to the register bank without REFCLK.
See the Update Clock Operation section of this document
for details.
Parallel I/O Operation
With the S/P SELECT pin tied high, the parallel I/O mode is
active. The I/O port is compatible with industry standard DSPs
and microcontrollers. Six address bits, eight bidirectional data
bits and separate write/read control inputs make up the I/O
port pins.
Parallel I/O operation allows write access to each byte of any
register in a single I/O operation at 100 MHz. Readback capability
for each register is included to ease designing with the AD9852.
Reads are not guaranteed at 100 MHz as they are intended for
software debug only.
Parallel I/O operation timing diagrams are shown in the Figures
49 and 50.
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| AD9852AST | CMOS 300 MHz Complete-DDS |
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| AD9853-65PCB | Programmable Digital OPSK/16-QAM Modulator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9852ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP |
| AD9852AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ C-DDS SYNTHESIZER - Bulk 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9852ASTZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASTZ | 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80 |
| AD9852ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
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