參數(shù)資料
型號(hào): AD9852ASQ
廠商: ANALOG DEVICES INC
元件分類: XO, clock
英文描述: CMOS 300 MHz Complete-DDS
中文描述: PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80
封裝: MS-026-BEC, LQFP-80
文件頁(yè)數(shù): 10/42頁(yè)
文件大小: 424K
代理商: AD9852ASQ
AD9852
–10–
REV. 0
Figures 14 and 15 show the effects of utilizing “sweet spots” in the tuning range of a DDS. Figure 14 represents a tuning word that
accentuates the aberrations associated with truncation in the DDS algorithm. Figure 15 is essentially the same output frequency (a few
tuning codes over), but it displays much fewer spurs on the output due to the selection of a tuning “sweet spot.” Consideration
should be given to all DDS applications to exploit the benefit of sweet spot tuning.
0
CENTER 112.499MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50kHz/
SPAN 500kHz
Figure 14. The Opposite of a “Sweet Spot.” 112.469 MHz
with multiple high energy spurs close around the
fundamental.
0
CENTER 112.469MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
50kHz/
SPAN 500kHz
Figure 15. A slight change in tuning word yields
dramatically better results. 112.499 MHz with all
spurs shifted out-of-band.
Figures 16 and 17 show the narrowband performance of the AD9852 when operating with a 20 MHz reference clock and the
REFCLK Multiplier enabled at 10
×
vs. a 200 MHz external reference clock.
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
Figure 16. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
200 MHz EXTCLK with REFCLK Multiplier Bypassed
0
CENTER 39.1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5kHz/
SPAN 50kHz
Figure 17. Narrowband SFDR, 39.1 MHz, 50 kHz BW,
10 MHz EXTCLK with REFCLK Multiplier = 10
×
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