參數(shù)資料
型號(hào)： AD9557BCPZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 32/92頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤(pán)
AD9557
Data Sheet
Rev. B | Page 38 of 92
WATCHDOG TIMER
The watchdog timer is a general-purpose programmable timer.
To set the timeout period, the user writes to the 16-bit watchdog
timer register (Address 0x0x0210 and Address 0x0211). A value
of 0b in this register disables the timer. A nonzero value sets the
timeout period in milliseconds (ms), giving the watchdog timer a
range of 1 ms to 65.535 sec. The relative accuracy of the timer is
approximately 0.1% with an uncertainty of 0.5 ms.
If enabled, the timer runs continuously and generates a timeout
event whenever the timeout period expires. The user has access
to the watchdog timer status via the IRQ mechanism and the
multifunction pins (M0 to M3). In the case of the multifunction
pins, the timeout event of the watchdog timer is a pulse that
lasts 32 system clock periods.
There are two ways to reset the watchdog timer (thereby
preventing it from causing a timeout event). The first is by
writing a Logic 1 to the autoclearing clear watchdog bit in the
reset functions register (Register 0x0A03, Bit 0). Alternatively,
the user can program any of the multifunction pins to reset the
watchdog timer. This allows the user to reset the timer by means
of a hardware pin rather than by using a serial I/O port operation.
EEPROM
EEPROM Overview
The AD9557 contains an integrated 2048-byte, electrically erasable,
programmable read-only memory (EEPROM). The AD9557
can be configured to perform a download at power-up via the
multifunction pins (M2 to M3), but uploads and downloads can
also be performed on demand via the EEPROM control registers
(Address 0x0E00 to Address 0x0E03).
The EEPROM provides the ability to upload and download
configuration settings to and from the register map. Figure 41
shows a functional diagram of the EEPROM.
Register 0x0E10 to Register 0x0E3F represent a 53-byte EEPROM
storage sequence area (referred to as the “scratch pad” in this
section) that enables the user to store a sequence of instructions
for transferring data to the EEPROM from the device settings
portion of the register map. Note that the default values for these
registers provide a sample sequence for saving/retrieving all of
the AD9557 EEPROM-accessible registers. Figure 41 shows
the connectivity between the EEPROM and the controller that
manages data transfer between the EEPROM and the register map.
The controller oversees the process of transferring EEPROM data
to and from the register map. There are two modes of operation
handled by the controller: saving data to the EEPROM (upload
mode) or retrieving data from the EEPROM (download mode).
In either case, the controller relies on a specific instruction set.
EEPROM
(0x000
TO 0x7FF)
DA
T
A
DA
T
A
DATA
EEPROM
ADDRESS
POINTER
M3
M2
REGISTER MAP
DEVICE
SETTINGS
(0x0A00 TO 0x0A0D)
SCRATCH PAD
(0x0E10 TO 0x0E3F)
SERIAL
INPUT/OUTPUT
PORT
C
O
N
D
IT
ION
(0
E0
1
[3
:0
])
SCRATCH PAD
ADDRESS
POINTER
DEVICE
SETTINGS
ADDRESS
POINTER
EEPROM
CONTROLLER
09
197-
024
Figure 41. EEPROM Functional Diagram
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