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參數(shù)資料
型號(hào)： AD9557BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/92頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告： Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤(pán)
AD9557
Data Sheet
Rev. B | Page 28 of 92
THEORY OF OPERATION
SPI/I2C
SERIAL PORT
EEPROM
REF MONITORING
AUTOMATIC
SWITCHING
÷N1
÷N2
÷N3
÷2
÷M0
OUT0
OUT1
10-BIT
INTEGER
DIVIDERS
MAX 1.25GHz
÷M1
×2
LF
PFD/CP
RF DIVIDER 1
÷3 TO ÷11
XO OR XTAL
XO FREQUENCIES
10MHz TO 180MHz
XTAL: 10MHz TO 50MHz
RF DIVIDER 2
÷3 TO ÷11
fOUT = 360kHz TO 1.25GHz
INTEGER DIVIDER
OUTPUT PLL (APLL)
FRAC1/
MOD1
17-BIT
INTEGER
24b/24b
RESOLUTION
DIGITAL PLL (DPLL)
÷2
REGISTER
SPACE
2kHz
T
O
1.
25G
Hz
R DIVIDER (20-BIT)
SYNC
RESET
PINCONTROL
M0 M1 M2 M3 IRQ
SPI/I2C
DIGITAL
LOOP
FILTER
TUNING
WORD
CLAMP AND
HISTORY
FREE RUN
TW
LF_VCO2
PFD/CP
LF
VCO2
3.35GHz
TO
4.05GHz
DP
F
D
30-
BI
T
NCO
ROM
AND
FSM
MULTIFUNCTION I/O PINS
(CONTROL AND STATUS
READBACK)
SYSTEM
CLOCK
PLL
÷2
AD9557
REFA
REFB
09197-
135
Figure 35. Detailed Block Diagram
OVERVIEW
The AD9557 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference, but with
jitter characteristics that are governed by the system clock, the
DCO, and the output PLL (APLL). The AD9557 supports up to
two reference inputs and input frequencies ranging from 2 kHz
to 1250 MHz. The core of this product is a digital phase-locked
loop (DPLL). The DPLL has a programmable digital loop filter
that greatly reduces jitter that is transferred from the active
reference to the output. The AD9557 supports both manual and
automatic holdover. While in holdover, the AD9557 continues
to provide an output as long as the system clock is present. The
holdover output frequency is a time average of the output
frequency history just prior to the transition to the holdover
condition. The device offers manual and automatic reference
switchover capability if the active reference is degraded or fails
completely. The AD9557 also has adaptive clocking capability
that allows the DPLL divider ratios to be changed while the
DPLL is locked.
The AD9557 has a system clock multiplier, a digital PLL (DPLL),
and an analog PLL (APLL). The input signal goes first to the DPLL,
which performs the jitter cleaning and most of the frequency
translation. The DPLL features a 30-bit digitally controlled
oscillator (DCO) output that generates a signal in the 175 MHz
to 200 MHz range. The DPLL output goes to an analog integer-N
PLL (APLL), which multiplies the signal up to the 3.35 GHz to
4.05 GHz range. That signal is then sent to the clock distribution
section, which has two divide-by-3 to divide-by-11 RF dividers
that are cascaded with 10-bit integer (divide-by-1 to divide-by-
1024) channel dividers.
The XOA and XOB inputs provide the input for the system clock.
These pins accept a reference clock in the 10 MHz to 600 MHz
range, or a 10 MHz to 50 MHz crystal connected directly across
the XOA and XOB inputs. The system clock provides the clocks
to the frequency monitors, the DPLL, and internal switching logic.
The AD9557 has two differential output drivers. Each driver has
a dedicated 10-bit programmable post divider. Each differential
driver is programmable either as a single differential or dual
single-ended CMOS output. The clock distribution section
operates at up to 1250 MHz.
In differential mode, the output drivers run on a 1.8 V power
supply to offer very high performance with minimal power
consumption. There are two differential modes: LVDS and 1.8 V
HSTL. In 1.8 V HSTL mode, the voltage swing is compatible
with LVPECL. If LVPECL signal levels are required, the designer
can ac-couple the AD9557 output and use Thevenin-equivalent
termination at the destination to drive the LVPECL inputs.
In single-ended mode, each differential output driver can
operate as two single-ended CMOS outputs. OUT0 supports
either 1.8 V or 3.3 V CMOS operation. OUT1 supports only
1.8 V operation.
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