參數(shù)資料
型號： 9S12KT256DGV1
英文描述： MC9S12KT256 Device User Guide
中文描述： MC9S12KT256設備用戶指南
文件頁數(shù)： 79/126頁
文件大小： 7307K
代理商： 9S12KT256DGV1
Device User Guide — 9S12KT256DGV1/D V01.09
79
Freescale Semiconductor
6.3 HCS12 Debug (DBG) Block Description
Consult the HCS12 DBG Block Guide for information about the Debug module.
6.4 HCS12 Interrupt (INT) Block Description
Consult the HCS12 INT Block Guide for information about the Interrupt module.
6.5 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the HCS12 MEBI Block Guide for information about the Multiplexed External Bus Interface
module.
6.6 HCS12 Module Mapping Control (MMC) Block Description
Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module.
Section 7 Analog to Digital Converter (ATD) Block
Description
Consult the ATD_10B16C Block Guide for further information about the A/D Converter module for the
MC9S12KG128(64)(32), MC9S12KL128(64) and MC9S12KC128(64). When the ATD_10B16C Block
Guide refers to
freeze mode
this is equivalent to
active BDM mode.
Consult the ATD_10B8C Block Guide for further information about the A/D Converter module for the
MC9S12KT256 and MC9S12KG256. When the ATD_10B8C Block Guide refers to
freeze mode
this is
equivalent to
active BDM mode.
Section 8 Clock Reset Generator (CRG) Block Description
Consult the CRG Block Guide for information about the Clock and Reset Generator module.
8.1 Device-specific information
The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the
VREG Block Guide for voltage level specifications.
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