參數(shù)資料
型號: 9S12KT256DGV1
英文描述: MC9S12KT256 Device User Guide
中文描述: MC9S12KT256設(shè)備用戶指南
文件頁數(shù): 119/126頁
文件大?。?/td> 7307K
代理商: 9S12KT256DGV1
Device User Guide — 9S12KT256DGV1/D V01.09
119
Freescale Semiconductor
32
D
NOACC hold time
t
NOH
2
32
33
D
PIPO0 delay time
t
P0D
2
7
33
34
D
PIPO0 valid time to E rise (PW
EL
–t
P0D
)
t
P0V
10
34
35
D
PIPO1 delay time
(1)
(PW
EH
-t
P1V
)
t
P1D
2
7
35
36
D
PIPO1 valid time to E fall
t
P1V
10
36
NOTES
:
1. Affected by clock stretch: add N x t
cyc
where N=0,1,2 or 3, depending on the number of clock stretches.
Table A-24 Expanded Bus Timing Characteristics
Conditions are shown in
Table A-4
unless otherwise noted, C
LOAD
= 50pF
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