參數(shù)資料
型號: 9S12KT256DGV1
英文描述: MC9S12KT256 Device User Guide
中文描述: MC9S12KT256設(shè)備用戶指南
文件頁數(shù): 71/126頁
文件大?。?/td> 7307K
代理商: 9S12KT256DGV1
Device User Guide — 9S12KT256DGV1/D V01.09
71
Freescale Semiconductor
Section 3 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1
shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
Figure 3-1 Clock Connections
CRG
Bus Clock
Core Clock
EXTAL
XTAL
Oscillator Clock
HCS12 CORE
Flash
BDM
OSC
CPU
MEBI
MMC
INT
DBG
IIC
RAM
SCI0, SCI1
PWM
ATD
EEPROM
TIM
SPI0, SPI1, SPI2
CAN0, CAN1, CAN4
PIM
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