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| 型號： | ZPSD611(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現場可編程微控制器外圍設備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數： | 58/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD611(V)E1 |
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ZPSD6XX(V) Family
12-58
PLD
Access
Recovery Time
to Normal
Access
PLD
Recovery Time
to Normal
Operation
Typical
Standby
Current
Propagation
Delay
Access
Time
Mode
Power Down
Normal tpd
(Note 1)
0
No Access
tLVDV
25μA
(Note 4)
Sleep
tLVDV2
(Note 2)
tLVDV3
(Note 3)
No Access
tLVDV1
10μA
(Note 5)
Table 31. Summary of ZPSD6XX(V) Timing and Standby Current During
Power Down and Sleep Mode
Power
Management
Unit
(cont.)
NOTES:
1. Power Down does not affect the operation of the ZPLD.The ZPLD operation in this mode is based
only on the ZPLD_Turbo Bit.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of tLVDV2.
3. PLD recovery time to normal operation after existing Sleep Mode. An input to the ZPLD during the
transition will have a propagation delay of tLVDV3.
4. Typical current consumption assuming CLKIN is disabled and the ZPLD Turbo bit is off.
5. Typical current consumption assuming CLKIN is disabled.
Sleep Mode
The Sleep Mode is activated if the Sleep mode bit, the APD bit and the ALE Polarity bit in
the PMMRs are set, and the APD Counter has overflowed after 15 CLKIN clocks
(see Figure 28). In Sleep Mode the ZPSD6XX(V) consumes less power than the Power
Down Mode, with typical I
CC
reduced to 10μA.
In this mode, the ZPLD still monitors the inputs and responds to them. As soon as the ALE
starts pulsing or the CSI input switches from high to low, the ZPSD6XX(V) exits the Sleep
Mode. The ZPSD6XX(V) access time from Sleep Mode is specified by tLVDV1. The ZPLD
response time to an input transition is specified by tLVDV2.
Port Function
Pin Level
MCU I/O
ZPLD Out
Address Out
Data Port
Peripheral I/O
No Change
No Change
Undefined
Three-State
Three-State
Table 30. Power Down Effect on Ports
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