參數(shù)資料
型號(hào): ZPSD611(V)E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,零功耗,4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞(可編程邏輯,零功耗,4K的位的SRAM,26余個(gè)可編程輸入/輸出,通用PLD的有63個(gè)輸入)
文件頁(yè)數(shù): 5/98頁(yè)
文件大?。?/td> 484K
代理商: ZPSD611(V)E1
ZPSD6XX(V) Family
12-5
PSDabel
PSDcompiler
PSDsimulator
PSDprogrammer
ZPLD DESCRIPTION
GENERATE ABEL FILE OR
USE DESIGN TEMPLATE
.OBJ FILE
CONFIGURE PSD
BUS INTERFACE
FITTER
ZPLD FITTING
PSDsilos III
CHIP SIMULATION
Magic Pro
III PROGRAMMER
CHIP PROGRAMMING
ADDRESS TRANSLATOR
EPROM MAPPING
PSDconfiguration
THIRD PARTY
PROGRAMMERS
PROGRAM CODE FILE
Figure 3. PSDsoft Development Tools
The ZPSD6XX(V) family is supported by the Windows-based PSDsoft Development
System. The PSDsoft design flow is shown in Figure 3. The ZPLD design entry is done
using PSDabel, which creates a minimized logic implementation, and provides logic
simulation of the ZPLDs. The ZPSD6XX(V) Bus Interface and I/O Port configuration are
entered in PSDconfiguration.
The PSDcompiler, comprised of a fitter and an address translator, generates an object
file from the PSDabel, PSDconfiguration and MCU code files. The object file is then
downloaded to a programmer (MagicPro III, Data I/O, or other third party programmer
for device programming) or to a PSDsimulator (PSDsilos III Logic simulator) for device-level
simulation.
Development
System
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