參數(shù)資料
型號： ZPSD611(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入）
文件頁數(shù)： 21/98頁
文件大?。?/td> 484K
代理商： ZPSD611(V)E1
ZPSD6XX(V) Family
12-21
Output Micro
Cell
Eight of the Output Micro
Cells are connected to Port C pins (except PC2) and are
named as McellC0-7. The remaining four Micro
Cells can be connected to Port A or Port B
and are named as McellAB4-7. If an McellAB output is not assigned to a specific pin in
PSDabel, the Micro
Cell Allocator will assign it to either Port A or B. Table 10 shows the
Micro
Cells and Port assignment.
Max
Data Bit for
Loading or
Reading in
8-Bit Mode 16-Bit Mode
Data Bit for
Loading or
Reading in
Native
Product
Terms
Borrowed
Product
Terms
Output
Micro
Cell Assignment
Port
McellC0
McellC1
McellC2
McellC3
McellC4
McellC5
McellC6
McellC7
McellAB4
McellAB5
McellAB6
McellAB7
Port C0
Port C1
*
Port C3
Port C4
Port C5
Port C6
Port C7
Port A4, B4
Port A5, B5
Port A6, B6
Port A7, B7
4
4
4
4
4
4
4
4
3
3
3
3
5
5
5
5
5
5
5
5
6
6
6
6
D0
D1
D2
D3
D4
D5
D6
D7
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D4
D5
D6
D7
Table 10. Output Micro
Cell Port and Data Bit Assignments
The Product Term Allocator
All Micro
Cells have the same basic cell architecture except McellC has four native
product terms and McellAB has three product terms. The GPLD also has a Product Term
Allocator with which the PSDcompiler can automatically borrow product terms from one
Micro
Cell to another. The McellC may borrow up to five product terms from other
Micro
Cells for a total of nine product terms. The McellAB has three native product terms
and can borrow up to six product terms. Borrowing allows Micro
Cell outputs needing
more product terms to use the unused product terms of others.
The architecture of the 12 Output Micro
Cells, as shown in Figure 8, consists of native
product terms and borrowed product terms from other Micro
Cells. The polarity of the
product term input is controlled by the XOR gate. The Micro
Cell can implement either
sequential logic, using the Flip-Flop element, or combinatorial functions. The multiplexer
selects the combinatorial or the sequential logic as the Micro
Cell output. The multiplexer
output can drive a Port pin and has also a feedback path to the AND array inputs.
Micro
Cell Flip-Flop Type
The Flip-Flop in the Micro
Cell can be configured as a D, Toggle, JK or SR type by using
PSDabel in PSDsoft. The Flip-Flop Clock, Preset and Clear inputs are driven from a product
term of the AND array. Alternatively, the device clock input (CLKIN) can be used for the
Flip-Flop. The Preset and Clear are active high inputs; the Flip-Flop is clocked by the rising
edge of the clock input.
ZPLDs
(cont.)
*
Internal node only.
相關(guān)PDF資料
PDF描述
ZPSD612(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
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