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參數(shù)資料
| 型號(hào)： | Z80B-CTC |
| 英文描述： | Z8 Microcontrollers |
| 中文描述： | Z8微控制器 |
| 文件頁數(shù)： | 45/222頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | Z80B-CTC |
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Z8 Microcontrollers
Reset—Watch-Dog Timer
ZiLOG
UM001600-Z8X0599
4-7
4.3 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot timer that resets the
Z8 if it reaches its terminal count. When operating in the
RUN or HALT modes, a WDT reset is functionally equiva-
lent to a hardware
POR
reset. The WDT is initially enabled
by executing the WDT instruction and refreshed on subse-
quent executions of the WDT instruction. The WDT cannot
be disabled after it has been initially enabled. Permanently
enabled WDTs are always enabled and the WDT instruc-
tion is used to refresh it. The WDT circuit is driven by an
on-board RC oscillator or external oscillator from the
XTAL1 pin. The POR clock source is selected with bit 4 of
the Watch-Dog Timer Mode register (WDTMR). In some
cases, a Z8 that offers the WDT but does not have a WDT-
MR register, has a fixed WDT timeout and uses the on
board RC oscillator as the only clock source. Please refer
to specific product specifications for selectability of time-
out, WDT during HALT and STOP modes, source of WDT
clock, and availability of the permanently-on WDT option.
Note:
Execution of the WDT instruction affects the Z
(zero), S (sign), and V (overflow) flags.
Note:
The WDTMR register is accessible only during the
first 60 processor cycles from the execution of the first
instruction after Power-On Reset, Watch-Dog Reset or a
Stop-Mode Recovery. After this point, the register cannot
be modified by any means, intentional or otherwise. The
WDTMR is a write-only register.
The WDTMR is located in Expanded Register File Bank F,
register 0FH. The control bits are described as follows:
WDT Time Select (D1, D0).
Bits 0 and 1 control a tap
circuit that determines the time-out period. Table 4-5
shows the different values that can be obtained. The de-
fault value of D1 and D0 are 0 and 1, respectively.
WDT During HALT (D2).
This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1. A WDT time out dur-
ing HALT mode will reset control register ports to their de-
fault reset conditions.
WDT During STOP (D3).
This bit determines whether
or not the WDT is active during STOP mode. Since XTAL
clock is stopped during STOP Mode, unless as specified
below, the on-board RC must be selected as the clock
source to the POR counter. A 1 indicates active during
STOP. The default is 1. If bits D3 and D4 are both set to 1,
the WDT only, is driven by the external clock during STOP
mode. This feature makes it possible to wake up from
STOP mode from an internal source. Please refer to spe-
cific product specifications for conditions of control and
port registers when the Z8 comes out of STOP mode. A
WDT time out during STOP mode will not reset all control
registers. The reset conditions of the ports from STOP
mode due to WDT time out is the same as if recovered us-
ing any of the other STOP mode sources.
Figure 4-5. Example of Z8 Watch-Dog Timer
Mode Register (Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDTMR (F) 0F
INT
WDT RC SYS
TAP* OSC CLK
00 5 128
01** 10 256
10 20 512
11 80 2048
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC
0 On-Board RC *
1 XTAL
Select for WDT
* Must be 0 for Z86C03
** Default setting after RESET
Reserved (Must be 0)
Table 4-5. Time-Out Period of the WDT
Typical
Time-Out of
Internal RC OSC
5 ms min
15 ms min
25 ms min
100 ms min
Time-Out of
D1
0
0
1
1
D0
0
1
0
1
SYS Clock
256TpC
512TpC
1024TpC
4096TpC
Notes:
TpC = XTAL clock cycle
The default on reset is, D0 = 1 and D1 = 0.
The values given are for VCC = 5.0V.
See the device product specification for exact WDTMR time
out select options available.
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