Z8 Microcontrollers
ZiLOG
Instruction Descriptions and Formats
UM001600-Z8X0599
12-75
TCM
TEST COMPLEMENT UNDER MASK
TCM
Test Complement Under Mask
TCM dst, src
Instruction Format:
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested
are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask). The
TCM instruction complements the destination operand, and then ANDs it with the source mask
(operand). The Zero (Z) Flag can then be checked to determine the result. If the Z Flag is set, then the
tested bits were 1. When the TCM operation is complete, the destination and source operands still
contain their original values.
Note:
Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the source or
destination Working Register operand is specified by adding 1110B (EH) to the high nibble of the
operand. For example, if Working Register R12 (CH) is the destination operand, then ECH will be used
as the destination operand in the Op Code.
dst
src
OPC
OPC
OPC
src
dst
dst
src
6
6
Cycles
OPC
(Hex)
Address
dst
Mode
src
62
63
r
r
r
Ir
10
10
64
65
R
R
R
IR
10
10
66
67
R
IR
IM
IM
Flags
:
C:
Z:
S:
V:
D:
H:
Unaffected
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to 0.
Unaffected
Unaffected
E
src
E
dst
or