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UM001600-Z8X0599
8-1
U
SER
’
S
M
ANUAL
C
HAPTER
8
P
OWER
-D
OWN
M
ODES
8.1 INTRODUCTION
In addition to the standard RUN mode, the Z8 MCU
sup-
ports two Power-Down modes to minimize device current
consumption. The two modes supported are HALT and
STOP.
8.2 HALT MODE OPERATION
The HALT mode suspends instruction execution and turns
off the internal CPU clock. The on-chip oscillator circuit re-
mains active so the internal clock continues to run and is
applied to the Counter/Timer(s) and interrupt logic.
To enter the HALT mode, it is necessary to first flush the
instruction pipeline to avoid suspending execution in mid-
instruction. To do this, the application program must exe-
cute a NOP instruction (opcode = FFH) immediately before
the HALT instruction (opcode 7FH), that is,
The HALT mode is exited by interrupts, either externally or
internally generated. Upon completion of the interrupt ser-
vice routine, the user program continues from the instruc-
tion after HALT.
The HALT mode may also be exited via a POR/RESET ac-
tivation or a Watch-Dog Timer (WDT) timeout. (See the
product data sheet for WDT availability). In this case, pro-
gram execution will restart at the reset restart address
000CH.
To further reduce power consumption in the HALT mode,
some Z8 family devices allow dynamic internal clock scal-
ing. Clock scaling may be accomplished on the fly by re-
programming bit 0 and/or bit1 of the STOP-Mode Recov-
ery register (SMR). See Figure 8-1.
Note:
Internal
Counter/Timer operation — adjustment of the prescaler
and downcounter values may be required. To determine
the actual HALT mode current (I
CC1
) value for the various
optional modes available, see the related Z8
device’s
product specification.
clock
scaling
directly
effects
FF
7F
NOP
HALT
;clear the instruction pipeline
;enter HALT mode