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| 型號(hào)： | Z80B-CTC |
| 英文描述： | Z8 Microcontrollers |
| 中文描述： | Z8微控制器 |
| 文件頁(yè)數(shù)： | 41/222頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | Z80B-CTC |
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Z8 Microcontrollers
Reset—Watch-Dog Timer
ZiLOG
UM001600-Z8X0599
4-3
After a reset, the first routine executed should be one that
initializes the control registers to the required system con-
figuration.
The
RESET
pin is the input of a Schmitt-triggered circuit.
Resetting the Z8 will initialize port and control registers to
their default states. To form the internal reset line, the out-
put of the trigger is synchronized with the internal clock.
The clock must therefore be running for
RESET
to function.
It requires 4 internal system clocks after reset is detected
for the Z8 to reset the internal circuitry. An internal pull-up,
combined with an external capacitor of 1 uf, provides
enough time to properly reset the Z8 (Figure 4-2). In some
cases, the Z8 has an internal POR timer circuit that holds
the Z8 in reset mode for a duration (T
POR
) before releasing
the device out of reset. On these Z8 devices, the internally
generated reset drives the reset pin low for the POR time.
Any devices driving the reset line must be open-drained in
order to avoid damage from possible conflict during reset
conditions. This reset time allows the on-board clock oscil-
lator to stabilize.
To avoid asynchronous and noisy reset problems, the Z8
is equipped with a reset filter of four external clocks
(4TpC). If the external reset signal is less than 4TpC in du-
ration, no reset occurs. On the fifth clock after the reset is
detected, an internal RST signal is latched and held for an
internal register count of 18 external clocks, or for the du-
ration of the external reset, whichever is longer. During the
reset cycle,
DS
is held active low while
AS
cycles at a rate
of the internal system clock. Program execution begins at
location 000CH, 5-10 TpC cycles after
RESET
is released.
For the internal Power-On Reset, the reset output time is
specified as T
POR
. Please refer to specific product specifi-
cations for actual values.
Figure 4-2. Example of External Power-On
Reset Circuit
1
μ
F
+5V
100 K
to
200 K
/RESET
K
10 V
Table 4-2. Expanded Register File Bank 0 Reset Values at RESET
Register
(HEX)
Register
Name
Port 0
Port 1
Port 2
Port 3
Bits
4
U
U
U
1
7
U
U
U
1
6
U
U
U
1
5
U
U
U
1
3
U
U
U
U
2
U
U
U
U
1
U
U
U
U
0
U
U
U
U
Comments
Input mode, output set to push-pull
Input mode, output set to push-pull
Input mode, output set to open drain
Standard Digital input and output
Z86L7X Family Device Port P34-P37 = 0
(Except Z86L70/71/75)
All other Z8 = 1
Undefined
00
01
02
03
04–EF
General-
Purpose
Registers
04-EF
U
U
U
U
U
U
U
U
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