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XRT94L33
xr
Rev.1.2.0.
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
262
STEP 2 – Set Bit 0 (Transmit RDI-P upon AIS-P) within the “Transmit SONET Path – RDI-P Control
Register – Byte 0”, as illustrated below.
Transmit SONET Path – RDI-P Control Register – Byte 0 (Address = 0xN9CB)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LOP-P RDI-P Code[2:0]
Transmit
RDI-P upon
LOP-P
AIS-P RDI-P Code[2:0]
Transmit
RDI-P upon
AIS-P
R/W
X
1
X
1
This step configures the Transmit SONET POH Processor block to automatically transmit the RDI-P indicator
(per the values written into Bits 3 through 1, within this register); anytime the corresponding “Receive SONET
POH Processor” block declares the “AIS-P” condition.
2.2.8.3.2.6
Configuring the Transmit SONET POH Processor block to automatically transmit RDI-
P, in response to declaration of the TIM-P Condition
The user can configure the Transmit SONET POH Processor block to automatically transmit the RDI-P
indicator, in response to the corresponding Receive SONET POH Processor block declaring the TIM-P
condition, by executing the following steps.
STEP 1 – Write the appropriate value into Bits 7 through 5 (TIM-P RDI-P Code[2:0]) within the
“Transmit SONET Path – RDI-P Condition Register – Byte 1; as illustrated below.
Transmit SONET Path – RDI-P Control Register – Byte 1 (Address = 0xN9CA)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIM-P RDI-P Code[2:0]
Transmit
RDI-P upon
TIM-P
UNEQ-P RDI-P Code[2:0]
Transmit
RDI-P upon
UNEQ-P
R/W
X
0
X
By writing this particular value into these bit-fields the user is specifying the value that the “Transmit SONET
POH Processor” block will set the RDI-P bit-fields (within the G1 byte of the outbound STS-1 frame) to
whenever the corresponding Receive SONET POH Processor block declares the TIM-P condition.
STEP 2 – Set Bit 4 (Transmit RDI-P upon TIM-P) within the “Transmit SONET Path – RDI-P Control
Register – Byte 1”; to “1” as illustrated below.
Transmit SONET Path – RDI-P Control Register – Byte 1 (Address = 0xN9CA)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TIM-P RDI-P Code[2:0]
Transmit
RDI-P upon
TIM-P
UNEQ-P RDI-P Code[2:0]
Transmit
RDI-P upon
UNEQ-P
R/W
X
1
X
This step configures the Transmit SONET POH Processor block to transmit the RDI-P indicator (per the
values written into Bits 3 through 1, within this register); anytime the corresponding “Receive SONET POH
Processor” block declares the “TIM-P” condition.