REV. 1.2.2 70 NOTICE EXAR Corporation reserves the right to make changes to the p" />
參數(shù)資料
型號(hào)： XR17D158IV-F
廠商： Exar Corporation
文件頁數(shù)： 68/73頁
文件大?。?/td> 0K
描述： IC UART PCI BUS OCTAL 144LQFP
產(chǎn)品培訓(xùn)模塊： UART Product Overview
標(biāo)準(zhǔn)包裝： 60
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
其它名稱： 1016-1292
XR17D158
xr
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
REV. 1.2.2
70
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet August 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
DATE
REVISION
DESCRIPTION
May 2003
1.0.0
Final Production Release. Updated AC and DC specifications. Clarified PCI
Burst Read and Write Transactions.
July 2003
1.1.0
Added Device Status to Ordering Information.
June 2004
1.2.0
Clarified pin descriptions- changed from using logic 1 and logic 0 to HIGH
(VCC) and LOW (GND) for input and output pin descriptions. Clarified Auto
RS485 and Sleep Mode description. Added timing diagram for external
clock input at XTAL1 pin (
Figure 19) and TECLK, TECH, and TECL to AC
Electrical Specifications. The Device Revision Register (DREV) has been
updated to 0x03 for devices with top mark date code "C2 YYWW".
November 2004
1.2.1
The Device Revision Register (DREV) has been updated to 0x09 for devices
with top mark date code "I2 YYWW".
August 2005
1.2.2
Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP"
to "LQFP" to be consistent with JEDEC and Industry norms.
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