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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR17V252
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
JULY 2008
REV. 1.0.2
GENERAL DESCRIPTION
The XR17V2521 (V252) is a single chip 2-channel
66MHz PCI UART (Universal Asynchronous Receiver
and
Transmitter)
solution,
optimized
for
higher
performance and lower power. The V252 device with
its fifth generation register set is designed to meet the
high
bandwidth
and
power
management
requirements for multi-serial communication ports for
system administration and management. The 32-bit
66MHz PCI interface is compliant with PCI 3.0 and
PCI power management revision 1.1 specifications.
The device provides an upgrade path for Exar’s
33MHz 5V and Universal PCI UART family.
The V252 consists of two independent UART
channels,
each
with
set
of
configuration
and
enhanced registers, 64 bytes of Transmit (TX) and
Receive (RX) FIFOs, and a fractional Baud Rate
Generator (BRG). A global interrupt source register
provides a complete interrupt status indication for
both channels to speed up interrupt parsing. The
V252 device operates at 33/66MHz and features fully
programmable TX and RX FIFO level triggers,
automatic hardware and software flow control, and
automatic RS-485 half duplex direction control output
for software and hardware design simplification.
NOTE 1: Covered by U.S. Patents #5,649,122 and #5,949,787
APPLICATIONS
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Instrumentation
Multi-port RS-232/RS-422/RS-485 Cards
Point-of-Sale Systems
FEATURES
High performance 32-bit 66MHz PCI UART
PCI 3.0 compliant
PCI power management rev. 1.1 compliant
EEPROM interface for PCI configuration
3.3V supply with 5V tolerant non-PCI (serial) inputs
Data read/write burst operation
Global interrupt register for both UART channels
Up to 8 Mbps serial data rate
Eight multi-purpose inputs/outputs
A 16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Two independent UART channels controlled with
■ 16C550 compatible register Set
■ 64-byte TX and RX FIFOs with level counters
and programmable trigger levels
■ Fractional baud rate generator
■ Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
■ Automatic Xon/Xoff software flow control
■ RS-485 half duplex direction control output
with selectable turn-around delay
Infrared (IrDA 1.0) data encoder/decoder
FIGURE 1. BLOCK DIAGRAM OF THE XR17V252
TMRCK
Device
Configuration
Registers
XTAL1
XTAL2
Crystal Osc / Buffer
TX0 , RX0 , DTR0#,
DSR0 #, RTS0#,
CTS0 #, CD0 #, RI0#
PCI Local
Bus
Interface
CLK( up to
66 MHz)
Configuration
Space
Registers
.
MPIO0 - MPIO7
Multi- purpose
Inputs/ Outputs
TX1 , RX1 , DTR1#,
DSR1 #, RTS1#,
CTS1 #, CD1 #, RI1#
16-bit
Timer/Counter
EECK
EEDI
EEDO
EECS
EEPROM
Interface
(5 V Tolerant
Serial Inputs)
ENIR
UART Channel 0
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
UART Channel 1
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
EN485#
3.3 V VCC
RST#
AD[31:0]
C/ BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
IDSEL
PERR#
SERR#
INTA#
PME#