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參數(shù)資料
| 型號(hào)： | XR17D158IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 5/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART PCI BUS OCTAL 144LQFP |
| 產(chǎn)品培訓(xùn)模塊： | UART Product Overview |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 8 |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1292 |
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xr
XR17D158
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
13
NOTE: RWR1=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-
Clear.
2.2
Device Configuration Register Set
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating
parameters to the D158 UART and for monitoring the status of various functions. The registers occupy 4K of
PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded
into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers
control or report on all 8 channel UARTs functions that include interrupt control and status, 16-bit general
purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset
control, and device identification and revision, and others.
The registers set is mapped into 8 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error flags.
0x2C
31:16
RWR1
Subsystem ID (write from external EEPROM by customer)
0x0000
15:0
RWR1
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x0000
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
0x34
31:0
RO
Reserved (returns zeros)
0x00000000
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
TABLE 2: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17D158IVTR-F | 制造商:Exar Corporation 功能描述:UART 8-CH 64Byte FIFO 5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17D158IVTR-F |
| XR17L152 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L152CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
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