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xr
XR17D158
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
55
TABLE 20: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
SPR
Bits 7-0 = 0xFF
FCTR
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
TXCNT
Bits 7-0 = 0x00
TXTRG
Bits 7-0 = 0x00
RXCNT
Bits 7-0 = 0x00
RXTRG
Bits 7-0 = 0x00
XCHAR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX[ch-7:0]
HIGH (if ENIR pin = LOW)
LOW (if ENIR pin = HIGH)
RTS#[ch-7:0]
HIGH
DTR#[ch-7:0]
HIGH
EECK
LOW
EECS
LOW
EEDI
LOW