參數(shù)資料
型號: W9425G6EH-5I
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 16M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 20/54頁
文件大?。?/td> 0K
代理商: W9425G6EH-5I
W9425G6EH
Publication Release Date:Dec. 03, 2008
- 27 -
Revision A08
9.6 AC Characteristics and Operating Condition
-4
-5/-5I
-6/-6I
SYM.
PARAMETER
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
UNIT NOTES
tRC
Active to Ref/Active Command Period
52
55
60
tRFC
Ref to Ref/Active Command Period
60
70
72
tRAS
Active to Precharge Command Period
36
70000
40
70000
42
100000
tRCD
Active to Read/Write Command Delay Time
16
15
18
tRAP
Active to Read with Auto-precharge Enable
16
15
nS
tCCD
Read/Write(a) to Read/Write(b) Command
Period
1
tCK
tRP
Precharge to Active Command Period
16
15
18
tRRD
Active(a) to Active(b) Command Period
8
10
12
tWR
Write Recovery Time
15
nS
tDAL
Auto-precharge Write Recovery + Precharge
Time
-
tCK
18
CL = 2
-
7.5
12
7.5
12
CL = 2.5
-
6
12
6
12
CL = 3
4
10
5
12
6
12
tCK
CLK Cycle Time
CL = 4
4
10
-
tAC
Data Access Time from CLK, CLK
-0.7
0.7
-0.7
0.7
tDQSCK
DQS Output Access Time from CLK, CLK
-0.6
0.6
-0.6
0.6
-0.6
0.6
16
tDQSQ
Data Strobe Edge to Output Data Edge Skew
0.4
0.45
nS
tCH
CLk High Level Width
0.45
0.55
0.45
0.55
0.45
0.55
tCL
CLK Low Level Width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
11
tHP
CLK Half Period (minimum of actual tCH, tCL)
min
(tCL,tCH)
min,
(tCL,tCH)
min,
(tCL,tCH)
tQH
DQ Output Data Hold Time from DQS
tHP
-0.5
tHP
-0.5
tHP
-0.5
nS
tRPRE
DQS Read Preamble Time
0.9
1.1
0.9
1.1
0.9
1.1
tRPST
DQS Read Postamble Time
0.4
0.6
0.4
0.6
0.4
0.6
tCK
11
tDS
DQ and DM Setup Time
0.4
0.45
tDH
DQ and DM Hold Time
0.4
0.45
tDIPW
DQ and DM Input Pulse Width (for each input) 1.75
1.75
nS
tDQSH
DQS Input High Pulse Width
0.35
tDQSL
DQS Input Low Pulse Width
0.35
tDSS
DQS Falling Edge to CLK Setup Time
0.2
tDSH
DQS Falling Edge Hold Time from CLK
0.2
tCK
11
tWPRES
Clock to DQS Write Preamble Set-up Time
0
nS
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