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參數資料
| 型號： | VSC7212RG |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 網絡接口 |
| 英文描述： | Gigabit Interconnect Chip |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, THERMALLY ENHANCED, CAVITY-DOWN, PLASTIC, TQFP-100 |
| 文件頁數： | 23/34頁 |
| 文件大?。?/td> | 504K |
| 代理商： | VSC7212RG |
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VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
04/10/01
Page 23
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 19: RCLK and RCLKN Timing Waveforms with
DUAL
= 1
Table 14: General Receive AC Characteristics
NOTE: (1) The probability of correct data acquisition and recovery is 95% per FC-PH 4.3 Section 5.3.
Parameters
Description
Min.
Max.
Units
Conditions
T
3
Delay between rising edge of
RCLK to rising edge of
RCLKN
RCLK to RCLKN skew
10 x T
RX
-500
10 x T
RX
+500
ps
T
RX
is the bit period of the
incoming data on Rx.
DT
3
-500
500
ps
Deviation of RCLK rising
edge to RCLKN rising edge.
Nominal delay is 10-bit
times.
T
4
Period of RCLK and
RCLKN
0.49 x
T
REFCLK
0.51 x
T
REFCLK
ps
Whether or not locked to
serial data, independent of
DUAL input.
DT
4
Deviation of
RCLK/RCLKN period from
REFCLK period
-1.0
1.0
%
Whether or not locked to
serial data, independent of
DUAL input.
T
R
, T
F
Output rise and fall time
—
2.4
ns
Between V
IL(MAX)
and
V
IH(MIN)
into 10pF load
ENDEC=1, recenter only
ENDEC=X, recenter + drift
8B/10B IDLE pattern,
Tested on a sample basis.
IEEE 802.3z Clause 38.68,
tested on a sample basis.
IEEE 802.3z Clause 38.69,
tested on a sample basis.
R
LAT
Latency from RX0 to
REFCLK or RCLK
70.5bc-1.6ns
48.5bc-1.6ns
81.5bc+4.1ns
102.5bc+4.1ns
bc+ns
T
LOCK(1)
Data acquisition lock time
—
2500
bc
T
JTD
Receive data Total
Jitter Tolerance (p-p)
Receive data Deterministic
Jitter Tolerance (p-p)
—
600
ps
D
JTD
—
370
ps
RCLKN
RCLK
T
4
T
3
Delay
f
baud
---10
T
3
±
=
T
RCLK
T
REFCLK
T
4
±
=
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