參數(shù)資料
型號(hào)： VSC7212RG
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： Gigabit Interconnect Chip
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, THERMALLY ENHANCED, CAVITY-DOWN, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 19/34頁(yè)
文件大?。?/td> 504K
代理商： VSC7212RG
VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
04/10/01
Page 19
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
VSC7214 MODE 1: RCLKEN=LOW, FLOCK=LOW, INDEP=HIGH
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to REFCLK, IDLE insertion/deletion is
enabled. The VSC7212 should be configured with RMODE(1:0)=00, FLOCK=0, and WSI=1. The WSI
connection inhibits chip-to-chip alignment, and allows IDLE insertion/deletion to occur independently in each
device.
VSC7214 MODE 2: RCLKEN=LOW, FLOCK=HIGH, INDEP=LOW
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to REFCLK, IDLE insertion/deletion is
disabled, and multiple receivers are word aligned. The VSC7212 should be configured with RMODE(1:0)=00,
FLOCK=1, and WSI connected to its own WSO or to the WSO of another VSC7212 if multiple devices are to
be used in parallel. The WSI connection allows word alignment to occur, and the FLOCK connection inhibits
IDLE insertion/deletion.
VSC7214 MODE 3: RCLKEN=LOW, FLOCK=HIGH, INDEP=HIGH
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to REFCLK, IDLE insertion/deletion is
disabled. The VSC7212 should be configured with RMODE(1:0)=00, FLOCK=1, and WSI=0. The WSI
connection inhibits chip-to-chip alignment, and the FLOCK connection inhibits IDLE insertion/deletion.
VSC7214 MODE 4: RCLKEN=HIGH, FLOCK=LOW, INDEP=LOW
This configuration does not require IDLE insertion/deletion, use Mode 6 instead.
VSC7214 MODE 5: RCLKEN=HIGH, FLOCK=LOW, INDEP=HIGH
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to RCLK/RCLKN, IDLE insertion/
deletion is enabled. The VSC7212 should be configured with RMODE(1:0)=10, FLOCK=0, and WSI=1. The
WSI connection inhibits chip-to-chip alignment, and allows IDLE insertion/deletion to occur.
VSC7214 MODE 6: RCLKEN=HIGH, FLOCK=HIGH, INDEP=LOW
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to RCLK/RCLKN, IDLE insertion/
deletion is disabled, and multiple receivers are word aligned. The VSC7212 should be configured with
RMODE(1:0)=10, FLOCK=1, and WSI connected to its own WSO. Multiple VSC7212 devices should not be
used in parallel when the outputs are synchronous to RCLK/RCLKN. The WSI connection allows word
alignment to occur, and the FLOCK connection inhibits IDLE insertion/deletion.
VSC7214 MODE 7: RCLKEN=HIGH, FLOCK=HIGH, INDEP=HIGH
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to RCLK/RCLKN, IDLE insertion/
deletion is disabled. The VSC7212 should be configured with RMODE(1:0)=10, FLOCK=1, and WSI=0. The
WSI connection inhibits chip-to-chip alignment, and the FLOCK connection inhibits IDLE insertion/deletion.
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