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參數(shù)資料
| 型號： | VSC7212RG |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Gigabit Interconnect Chip |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, THERMALLY ENHANCED, CAVITY-DOWN, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 504K |
| 代理商： | VSC7212RG |
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VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 14
G52268-0, Rev 3.3
04/10/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Receiver State Machine
The VSC7212 contains a Loss of Synchronization State Machine (LSSM) which is responsible for
detecting and handling loss of bit and word clock synchronization in a controlled manner. There are three states
in the LSSM: LOSS_OF_SYNC, RESYNC and SYNC_ACQUIRED as shown in the state diagram of Figure 9.
The RESYNC state is entered when a 10-bit word has been received which contains the 7-bit
“
Comma
”
pattern
(e.g., a K28.5 IDLE character). After entering the RESYNC state, the VSC7212 will stay in it until a valid,
“
non-Comma
”
transmission is received, then it transitions to the SYNC_ACQUIRED state indicating a normal
operating condition. The RESYNC state is re-entered if four consecutive
“
Commas
”
are received or if a single
“
Comma
”
is received that changes the 10B character framing boundary. The LOSS_OF_SYNC state is entered
whenever four consecutive invalid transmissions have been detected or when the occurrences of invalid
transmission outnumber those of valid transmission by four. The relative occurrences of invalid vs. valid
transmissions are monitored with a simple up/down counter that increments when an invalid transmission is
detected and decrements otherwise. The LSSM transitions to the LOSS_OF_SYNC state when the counter
reaches four, and the counter is reset. A state diagram for the invalid transmission counter is shown in
Figure 10. The VSC7212 receiver will stay in the LOSS_OF_SYNC state until a valid
“
Comma
”
pattern is
detected. Note that the RESYNC state is entered whenever the 10B framing boundary is changed, and whenever
the Word Sync Sequence is received. When ENDEC is LOW, the LSSM logic is disabled.
Figure 9: State Diagram of the Loss of Synchronization State Machine
RESYNC
IDLE
=1
ERR
=1
KCH
=1
Four Consecutive
Invalid Transmissions
or
Valid
“
Comma
”
(K28.1, K28.5, K28.7)
Valid
“
Non-Comma
”
Invalid minus Valid
Transmissions is > 4
LOSS_OF_SYNC
IDLE
=0
ERR
=1
KCH
=1
Valid
“
Comma
”
Invalid Transmission
SYNC_ACQUIRED
IDLE
=X
ERR
=0
KCH
=X
IDLE
=X
ERR
=1
KCH
=0
or
Four Consecutive
“
Commas
”
or
Mis-Aligned
“
Comma
”
相關(guān)PDF資料 |
PDF描述 |
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| VSC7216-01 | Multi-Gigabit Interconnect Chip |
| VSC7216-02 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PLQP0064GA-A (64P6U-A) |
| VSC7217 | Multi-Gigabit Interconnect Chip |
| VSC7226 | 740; 38000/740 Series; Microcontroller; Bit Size: 8-bit; ROM: 60K; RAM: 2048; ROM Type: Mask ROM; CPU: 740 core; Minimum Instruction Execution Time (ns): 240 (@16.8MHz); Operating Frequency / Supply Voltage: 1.8 to 5.5V; Operating Ambient Temperature (°C): -20 to 85; Package Code: PRDP0064BA-A (64P4B) |
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| VSC7216-01 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Gigabit Interconnect Chip |
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| VSC7216UC-01 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Gigabit Interconnect Chip |
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