參數(shù)資料
型號(hào)： VSC7212RG
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： Gigabit Interconnect Chip
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, THERMALLY ENHANCED, CAVITY-DOWN, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 17/34頁(yè)
文件大?。?/td> 504K
代理商： VSC7212RG
VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
04/10/01
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 11: Parallel Loopback Mode Operation
Built-In Self Test Operation
Built-In Self Test operation is enabled when the BIST input is HIGH, which causes TMODE(2:0) to be
internally set to 000. Upon entering BIST mode, the transmitter will issue a Word Sync Sequence in order to
recenter the elasticity buffers in the receive channel. Then the transmitter repeatedly sends a simple 256-byte
incrementing data pattern (prior to 8B/10B encoding) followed by three IDLE characters (K28.5). Note that this
incrementing pattern plus three IDLEs will cause both disparities of each data character and the IDLE character
to be transmitted, and contains a sufficient IDLE density for any application requiring IDLE insertion/deletion.
It is up to the user to enable IDLE insertion/deletion if the receiver
’
s word clock is not frequency locked to the
transmitter
’
s REFCLK.
The receiver monitors incoming data for this pattern and indicates if any errors are detected. Correct
reception of the pattern is reported on each receiver
’
s TBERR output, a LOW means the pattern is being
received correctly and a HIGH means that errors are detected. When BIST transitions from LOW to HIGH,
each TBERR output is initialized HIGH. It will be cleared LOW whenever one or more IDLE characters
followed by all 256 data characters are sequentially received without error, and set HIGH whenever a pattern
mis-match or receiver error is encountered. Received data and associated status will be output as in normal
operation. Please note that Serial Loopback mode and receiver output timing mode selection via RMODE(1:0)
operate independently of BIST mode, but BIST mode disables Parallel Loopback mode.
Figure 12: BIST Mode Operation
10
Encode
8B/10B
D Q
T(7:0)
C/D
WSEN
8
8
PTX-
RTX+
RTXEN
PTXEN
PRX-
RRX+
RXP/R
LBEN(1:0)
Recovery
Clk/Data
Decode
8B/10B
10
Buffer
Elastic
3
8
IDLE
KCH
ERR
R(7:0)
8
TRANSMITTER
RECEIVER
LBTX
RSDET
a
REFCLK
LBTX
1
0
KCHAR
PARLOOP
a
REFCLK
1
0
1
0
(dec)
10
Encode
8B/10B
D Q
T(7:0)
C/D
WSEN
a
REFCLK
8
8
PTX-
RTX+
RTXEN
PTXEN
PRX-
RRX+
RXP/R
LBEN(1:0)
Recovery
Clk/Data
Decode
8B/10B
10
Buffer
Elastic
3
8
IDLE
KCH
ERR
R(7:0)
8
TRANSMITTER
RECEIVER
LBTX
RSDET
WORDCLK
0
KCHAR
BIST
1
0
1
0
Gen
BIST
Chk
BIST
CGERR
1
0
BIST
From Tx
Clock Gen
}
TBERR
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