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參數(shù)資料
| 型號： | VSC7212RG |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Gigabit Interconnect Chip |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, THERMALLY ENHANCED, CAVITY-DOWN, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 22/34頁 |
| 文件大?。?/td> | 504K |
| 代理商： | VSC7212RG |
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VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Page 22
G52268-0, Rev 3.3
04/10/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 17: Receive Output Timing Waveforms with
RMODE
= 00 or 01
Table 12: Receive Output AC Characteristics with
RMODE
= 00 or 01
Figure 18: Receive Output Timing Waveforms with
RMODE
= 10 or 11
Table 13: Receive Output AC Characteristics with
RMODE
= 10 or 11
Parameters
Description
Min
Max
Units
Conditions
T
CQ
REFCLK Rising Edge to TTL
Output Transition
REFCLK Rising Edge to TTL
Output Transition
TTL Output Transition to
REFCLK Rising Edge
2.58 ns - 0 bc
5.43 ns - 0 bc
ns
RMODE = 00
bc = Bit Clock
RMODE = 01
bc = Bit Clock
T
CQ
2.58 ns - 2 bc
5.43 ns - 2 bc
ns
T
QC
T
PER
-
T
CQ_max
T
PER
-
T
CQ_min
ns
Parameters
Description
Min
Max
Units
Conditions
T
CQ
RCLK/RCLKN Rising Edge to
TTL Output Transition
TTL Output Transition to RCLK/
RCLKN Rising Edge
RCLK/RCLKN Duty Cycle
-1.25 ns + 4 bc
1.25 ns + 4 bc
ns
RMODE = 10 or 11
bc = Bit Clock
T
QC
T
PER
-
T
CQ_max
50% - 1 ns
T
PER
-
T
CQ_min
ns
DC
50% + 1 ns
ns
Measured at 1.4 V
REFCLK
(DUAL = 0)
R(7:0), TBERR
KCH, IDLE, ERR
PSDET, RSDET
Valid
Valid
Valid
T
CQ_max
T
CQ_min
REFCLK
(DUAL = 1)
T
QC_min
T
PER
RCLK
(DUAL = 0)
R(7:0), TBERR
KCH, IDLE, ERR
PSDET, RSDET
Valid
Valid
Valid
T
CQ_max
T
CQ_min
RCLK/RCLKN
(DUAL = 1)
T
QC_min
T
PER
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