參數(shù)資料
型號(hào)： VSC7212RG
廠商： VITESSE SEMICONDUCTOR CORP
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： Gigabit Interconnect Chip
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, THERMALLY ENHANCED, CAVITY-DOWN, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 21/34頁(yè)
文件大小： 504K
代理商： VSC7212RG
VITESSE
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
G52268-0, Rev 3.3
04/10/01
Page 21
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800)-VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 15: Transmit Input Timing Waveforms with
TMODE
= 11X (
“
ASIC-Friendly
”
Timing)
Table 10: Transmit Input AC Characteristics with
TMODE
= 11X
Figure 16: Transmit Serial Timing Waveforms
Table 11: Transmit Serial AC Characteristics
Parameters
Description
Min
Max
Units
Conditions
T
S
Input Skew relative to the rising
edge of TBC
—
2.0
bc
Measured between the valid data
level of the input and the 1.4V point
of TBC
Parameters
Description
Min
Max
Units
Conditions
T
SDR,
T
SDF
TX+/- rise and fall time
—
330
ps
Between V
OL(MAX)
and
V
OH(MIN)
ENDEC=1 TMODE=000
ENDEC=1 TMODE=10X
IEEE 802.3z Clause 38.69,
Tested on a sample basis
IEEE 802.3z Clause 38.69,
Tested on a sample basis
T
LAT
Latency, REFCLK to TX0
Latency, TBC to TX0
Serial data output
Total Jitter (p-p)
Serial data output
Deterministic Jitter (p-p)
22bc+0.2ns
36bc+0.0ns
22bc+0.8ns
38bc+0.3ns
bc + ns
T
J
—
192
ps
T
DJ
—
80
ps
Valid
T
S
Valid
Valid
T
S
Internal Clock
(from PLL)
TBC
T(7:0)
C/D
WSEN
T
SDR,
T
SDF
T
LAT
TX+, TX-
TX0
Internal Clock
(from PLL)
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