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參數(shù)資料
| 型號： | USB97CFDC-MN |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | USB FLOPPY DISK CONTROLLER |
| 中文描述： | 1 Mbps, FLOPPY DISK DRIVE CONTROLLER, PQFP100 |
| 封裝： | 12 X 12 MM, TQFP-100 |
| 文件頁數(shù)： | 26/59頁 |
| 文件大?。?/td> | 385K |
| 代理商： | USB97CFDC-MN |
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SMSC DS – USB97C201
Page 26
Rev. 03/25/2002
PRELIMINARY
Table 17 - Utility Configuration Register
UTIL_CONFIG
(9D RESET=0x00)
NAME
R/W
SRAMSW
R/W
UTILITY CONFIGURATION REGISTER
DESCRIPTION
1 = The 768 byte SRAM is located at 0x0400-
0x06FF in the Code Space, instead of
external Memory.
0 = The 768 byte SRAM is located at 0x0400-
0x06FF in the XDATA space.
Reserved. This bit should never be written to
a “1”.
1 = GPIO0 Output Auto Toggle enabled.
0 = Disabled, normal operation occurs.
GPIO4/SOF Output Select Mux
0 = GPIO4
1 = The IDE_nIOW signal is output.
P3.5 Timer 1 input trigger source
0 = GPIO3
1 = TBD
P3.4 Timer 0 input trigger source
0 = GPIO2
1 = TBD
GPIO1/TXD Output Select Mux
0 = GPIO1
1 = P3.1
P3.0 RXD/GPIO0 Input Select Mux
0 = RXD<=GPIO0
1 = RXD<='0'
BIT
7
6
Reserved
R/W
5
GPIO0_TOG
R/W
4
GPIO4/nWE
R/W
3
GPIO3/T1
R/W
2
GPIO2/T0
R/W
1
GPIO1/TXD
R/W
0
GPIO0/RXD
R/W
Note 1:
GPIO0, when used as an output, will automatically toggle with 1second period and 50% duty cycle if
GPIO0_TOG is high.
Table 18 – SRAM Data Port Register
SRAM_DATA
(0x9F- RESET=0x00)
NAME
R/W
SRAM_DATA
[7:0]
SRAM DATA PORT
REGISTER
BIT
[7:0]
DESCRIPTION
R/W
Data to be read or written
from/to the buffer SRAM. The
address
of
determined
SRAM_ADD1/2 registers. Data
to be written will be done so
upon write of this register.
While reads of the register
always reflects the data at the
memory location.
the
data
is
by
the
Table 19 – SRAM Address Register 1
SRAM_ADD1
(A1 RESET=0x00)
NAME
R/W
SRAM_ADD
[7:0]
SRAM ADDRESS REGISTER 1
BIT
[7:0]
DESCRIPTION
R/W
This register contains lower bits
of the address in the buffer
RAM that the SRAM_DATA
register reads or writes.
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