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參數(shù)資料
| 型號： | USB97CFDC-MN |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | USB FLOPPY DISK CONTROLLER |
| 中文描述： | 1 Mbps, FLOPPY DISK DRIVE CONTROLLER, PQFP100 |
| 封裝： | 12 X 12 MM, TQFP-100 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 385K |
| 代理商： | USB97CFDC-MN |
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SMSC DS – USB97C201
Page 20
Rev. 03/25/2002
PRELIMINARY
Table 7 - Interrupt 0 Mask
IMR_0
(0x93- RESET=0xFF)
NAME
USB_STAT
INTERRUPT 0 MASK REGISTER
DESCRIPTION
USB Bus System Event interrupt mask
0 = Enable Interrupt
1 = Mask Interrupt
SETUP interrupt mask
0 = Enable Interrupt
1 = Mask Interrupt
Reserved.
External ATA-66 interrupt input mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer B Output Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer A Output Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer B Input Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SRAM Buffer A Input Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
BIT
7
R/W
R/W
6
SETUP
R/W
5
4
Reserved
ATA_IRQ
R/W
R/W
3
RAMRD_B
R/W
2
RAMRD_A
R/W
1
RAMWR_B
R/W
0
RAMWR_A
R/W
Note1:
The mask bits do not prevent the status in the ISR_0 register from being set, only from generating an
interrupt.
Table 8 - Interrupt 1 Source Register
ISR_1
(0x90- RESET=0x00)
BIT
NAME
R/W
7
ZLP_EP0
R/W
1= A ZLP has been received on EP0RX.
6
Reserved
R
This bit always reads a “0”.
5
ATA_PIO
R
This bit reflects that state of the PIO_COMPLETE bit (bit 6) of
the ATA_CTL register. It cannot be written directly.
4
EP1RX
R/W
1 = A Packet was successfully received on Endpoint 1 and
stored in the Buffer SRAM. OUT tokens will be NAK’d until this
bit is cleared.
3
EP1TX
R/W
1 = A Packet was successfully transmitted on Endpoint 1 from
the Buffer SRAM. IN tokens will be NAK’d until this bit is
cleared.
2
EP0RX
R/W
1 = A non-SETUP, non ZLP Packet (see ISR_0 SETUP bit)
was successfully received on Endpoint 0 and stored in the
Buffer SRAM. OUT tokens will be NAK’d until this bit is
cleared.
1
EP0TX
R/W
1 = A Packet was successfully transmitted on Endpoint 0 from
the Buffer SRAM. IN tokens will be NAK’d until this bit is
cleared.
0
SUSPEND
R/W
Suspend – If 3ms of IDLE state are detected by the hardware,
then this bit will be set.
INTERRUPT 1 SOURCE REGISTER
DESCRIPTION
Note 1:
The bits (except for bit 5)in this register are cleared by writing a ‘1’ to the corresponding bit. If not masked by
the corresponding bit in the IMR1 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s
external INT1 input.
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相關(guān)代理商/技術(shù)參數(shù) |
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| USB-A(M)-A(F)-1M-BEIGE | 制造商:SMART CABLE 功能描述: |
| USB-A-001A | 制造商:YAMAICHI 制造商全稱:Yamaichi Electronics Co., Ltd. 功能描述:Universal Serial Bus, Type A - 90° Receptacle |
| USB-A-001A-30 | 制造商:YAMAICHI 制造商全稱:Yamaichi Electronics Co., Ltd. 功能描述:Universal Serial Bus, Type A - 90° Receptacle |
| USB-A-002A | 制造商:YAMAICHI 制造商全稱:Yamaichi Electronics Co., Ltd. 功能描述:Universal Serial Bus, Type A - 90° Receptacle |
| USB-A-002A-30 | 制造商:YAMAICHI 制造商全稱:Yamaichi Electronics Co., Ltd. 功能描述:Universal Serial Bus, Type A - 90° Receptacle |
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