
CHAPTER 22 STANDBY FUNCTION
User’s Manual U16890EJ1V0UD
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22.6 Subclock Operation Mode
22.6.1 Setting and operation status
The subclock operation mode is set when the PCC.CK3 bit is set to 1 in the normal operation mode.
When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system
operates only with the subclock.
Table 22-8 shows the operation status in subclock operation mode.
In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal
operation mode because the subclock is used as the internal system clock. In addition, the power consumption can
be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator.
Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0
bits (using a bit manipulation instruction to manipulate the bit is recommended). For details,
refer to 6.3 (1) Processor clock control register (PCC).
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
conditions are satisfied and set the subclock operation mode.
Main clock (f
XX
) > Subclock (f
XT
: 32.768 kHz)
×
4
22.6.2 Releasing subclock operation mode
The subclock operation mode is released when the CK3 bit is cleared to 0 or by reset (RESET pin input,
WDTRES1, WDTRES2 signal). If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation
stabilization time of the main clock by software, and clear the CK3 bit to 0.
The normal operation mode is restored when the subclock operation mode is released.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit
manipulation instruction to manipulate the bit is recommended). For details, refer to 6.3 (1)
Processor clock control register (PCC).