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CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U16890EJ1V0UD
203
6.4 Operation
6.4.1 Operation of each clock
The following table shows the operation status of each clock.
Table 6-1. Operation Status of Each Clock
PCC Register
CLS bit = 0,
MCK bit = 0
CLS bit = 1,
MCK bit = 0
CLS bit = 1,
MCK bit = 1
Register Setting and
Operation Status
Target Clock
During
reset
During
oscillation
stabilization
time count
HALT
mode
IDLE
mode
STOP
mode
Subclock
mode
Sub-IDLE
mode
Subclock
mode
Sub-IDLE
mode
Main clock oscillator (f
X
)
×
{
{
{
×
{
{
×
×
Subclock oscillator (f
XT
)
{
{
{
{
{
{
{
{
{
CPU clock (f
CPU
)
×
×
×
×
×
{
×
{
×
Internal system clock (f
CLK
)
×
×
{
×
×
{
×
{
×
Peripheral clock (f
XX
to f
XX
/1024)
×
×
{
×
×
{
×
×
×
WT clock (main)
×
{
{
{
×
{
{
×
×
WT clock (sub)
{
{
{
{
{
{
{
{
{
WDT1 clock (f
XW
)
×
{
{
{
×
{
{
×
×
WDT2 clock (main)
×
×
{
×
×
{
×
×
×
WDT2 clock (sub)
{
{
{
{
{
{
{
{
{
Remark
O: Operable
×
: Stopped
6.4.2 Clock output function
The clock output function is used to output the internal system clock (f
CLK
) from the CLKOUT pin.
The internal system clock (f
CLK
) is selected by using the PCC.CK3 to PCC.CK0 bits.
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the
control register of port CM.
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the
clock when it is in the operable status. It outputs a low level in the stopped status. However, the port mode (PCM1:
input mode) is selected until the CLKOUT pin output is set after reset. Consequently, the CLKOUT pin goes into a
high-impedance state.
6.4.3 External clock input function
An external clock can be directly input to the oscillator. Input the clock to the X1 pin and its inverse signal to the X2
pin. Set the PCC.MFRC bit to 1 (on-chip feedback resistor not used). Note, however, that oscillation stabilization time
is inserted even in the external clock mode. Connect V
DD
directly to the REGC pin.