![](http://datasheet.mmic.net.cn/370000/UPD703201_datasheet_16740720/UPD703201_80.png)
Preliminary Product Information U15436EJ1V0PM
80
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) In separate bus mode
(a) Read cycle (CLKOUT asynchronous): In separate bus mode
(T
A
=
–
40 to +85
°
C, V
DD
= AV
DD
= EV
DD
= V
DD
BU = 2.2 to 2.7 V, V
SS
= AV
SS
= EV
SS
= V
SS
BU = 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to RD
↓
)
t
SARD
<52>
0.5T
–
15
ns
Address hold time (from RD
↑
)
t
HARD
<53>
2
ns
RD low-level width
t
WRDL
<54>
(1.5 + n) T
–
10
ns
Data setup time (to RD
↑
)
t
SISD
<55>
20
ns
Data hold time (from RD
↑
)
t
HISD
<56>
0
ns
Data setup time (to address)
t
SAID
<57>
(2 + n) T
–
25
ns
t
SRDWT1
<58>
0.5T
–
20
ns
WAIT setup time (to RD
↓
)
t
SRDWT2
<59>
(0.5 + n) T
–
20
ns
t
HRDWT1
<60>
0.5T
ns
WAIT hold time (from RD
↓
)
t
HRDWT2
<61>
(0.5 + n) T
ns
t
SAWT1
<62>
T
–
20
ns
WAIT setup time (to address)
t
SAWT2
<63>
(1 + n) T
–
20
ns
t
HAWT1
<64>
T
ns
WAIT hold time (from address)
t
HAWT2
<65>
(1 + n) T
ns
Remarks 1.
T = 1/f
CPU
(f
CPU
: CPU operation clock frequency)
n: Number of wait clocks inserted in bus cycle
The sampling timing changes when a programmable wait is inserted.
The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input
from X1.
2.
3.
(b) Read cycle (CLKOUT synchronous): In separate bus mode
(T
A
=
–
40 to +85
°
C, V
DD
= AV
DD
= EV
DD
= V
DD
BU = 2.2 to 2.7 V, V
SS
= AV
SS
= EV
SS
= V
SS
BU = 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
↑
to address, CS t
DKSA
<66>
0
19
ns
Data input setup time (to CLKOUT
↑
)
t
SISDK
<67>
15
ns
Data input hold time (from CLKOUT
↑
)
t
HKISD
<68>
5
ns
Delay time from CLKOUT
↓↑
to RD
t
DKSR
<69>
0
19
ns
WAIT setup time (to CLKOUT
↑
)
t
SWTK
<70>
15
ns
WAIT hold time (from CLKOUT
↑
)
t
HKWT
<71>
5
ns
Remark
The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from
X1.