參數(shù)資料
型號： UPD703201
廠商： NEC Corp.
英文描述： 32-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 32位單晶片微控制器
文件頁數(shù)： 33/98頁
文件大?。?/td> 797K
代理商： UPD703201
Preliminary Product Information U15436EJ1V0PM
33
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 6-1. Interrupt Source List (2/2)
Type
Classifi-
cation
Default
Priority
Name
Trigger
Genera-
ting Unit
Exception
Code
Handler
Address
Restored
PC
Interrupt
Control
Register
17
INTTM4
Match between TM4 and
CR4/TM4 overflow
TM4
0190H
00000190H
nextPC
TMIC4
18
INTTM5
Match between TM5 and
CR5/TM5 overflow
TM5
01A0H
000001A0H
nextPC
TMIC5
19
INTCSI0
CSI0 transfer end
CSI0
01B0H
000001B0H
nextPC
CSIIC0
20
INTIIC
Note 1
I
2
C transfer end
I
2
C
01C0H
000001C0H
nextPC
IICIC0
21
INTCSI1
CSI1 transfer end
CSI1
01D0H
000001D0H
nextPC
CSIIC1
22
INTSRE0
UART0 receive error
UART0
01E0H
000001E0H
nextPC
SREIC0
23
INTSR0
UART0 receive end
UART0
01F0H
000001F0H
nextPC
SRIC0
24
INTST0
UART0 transfer end
UART0
0200H
00000200H
nextPC
STIC0
25
INTCSI2
CSI2 transfer end
CSI2
0210H
00000210H
nextPC
CSIIC2
26
INTSRE1
UART1 receive error
UART1
0220H
00000220H
nextPC
SREIC1
27
INTSR1
UART1 receive end
UART1
0230H
00000230H
nextPC
SRIC1
28
INTST1
UART1 transmit end
UART1
0240H
00000240H
nextPC
STIC1
29
INTCSI3
CSI3 transfer end
CSI3
0250H
00000250H
nextPC
CSIIC3
30
INTCSI4
Note 2
CSI4 transfer end
CSI4
0260H
00000260H
nextPC
CSIIC4
31
INTAD
A/D conversion end
ADC
0270H
00000270H
nextPC
ADIC
32
INTDMA0
DMA0 transfer end
DMA
0280H
00000280H
nextPC
DMAIC0
33
INTDMA1
DMA1 transfer end
DMA
0290H
00000290H
nextPC
DMAIC1
34
INTDMA2
DMA2 transfer end
DMA
02A0H
000002A0H
nextPC
DMAIC2
35
INTDMA3
DMA3 transfer end
DMA
02B0H
000002B0H
nextPC
DMAIC3
36
INTROV
RTC overflow
RTC
02C0H
000002C0H
nextPC
ROVIC
Maskable
Interrupt
37
INTBRG
BRG match
BRG
02D0H
000002D0H
nextPC
BRGIC
Note
1.
Valid for the
μ
PD703201Y, 70F3201Y, 703204Y and 70F3204Y only.
2.
Valid for the V850E/SA3 only.
Remarks1.
Default Priority:
Priority that applies when two or more maskable interrupt requests occur at the
same time. The highest priority is 0.
The value of the PC saved to EIPC or FEPC when interrupt servicing/exception
processing is started. However, the value of the restored PC saved when an
interrupt is acknowledged during division instruction (DIV, DIVH, DIVU, DIVHU)
execution is the value of the PC of the current instruction (DIV, DIVH, DIVU,
DIVHU).
The value of the PC to be processed after an interrupt/exception.
The execution address of the illegal instruction when an illegal op code exception occurs is
calculated with (Restored PC
4).
Restored PC:
nextPC:
2.
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相關(guān)代理商/技術(shù)參數(shù)
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