![](http://datasheet.mmic.net.cn/370000/UPD703201_datasheet_16740720/UPD703201_60.png)
Preliminary Product Information U15436EJ1V0PM
60
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(4/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
OR
reg1,reg2
rrrrr001000RRRRR
GR[reg2]
←
GR[reg2]OR GR[reg1]
1
1
1
0
×
×
ORI
imm16,reg1,reg2
rrrrr110100RRRRR
i i i i i i i i i i i i i i i i
GR[reg2]
←
GR[reg1]OR zero-extend(imm16)
1
1
1
0
×
×
list12,imm5
00000 1111 0iiiiiL
LLLLLLLLLLL00001
Store-memory(sp–4,GR[reg in list12],Word)
sp
←
sp–4
repeat 1 step above until all regs in list12 is stored
sp
←
sp-zero-extend(imm5)
n+1
Note 4
n+1
Note 4
n+1
Note 4
PREPARE
list12,imm5,
sp/imm
Note 14
00000 1111 0iiiiiL
LLLLLLLLLLLff011
imm16/imm32
Note 15
Store-memory(sp–4,GR[reg in list12],Word)
sp
←
sp–4
repeat 1 step above until all regs in list12 is stored
sp
←
sp-zero-extend(imm5)
ep
←
sp/imm
n+2
Note 4
Note 16
n+2
Note 4
Note 16
n+2
Note 4
Note 16
RETI
0000011111100000
0000000101000000
if PSW.EP=1
then PC
PSW
←
EIPSW
else if PSW.NP=1
then
←
EIPC
PC
PSW
←
FEPSW
PC
←
EIPC
PSW
←
EIPSW
←
FEPC
else
3
3
3
R
R
R
R
R
reg1,reg2
rrrrr111111RRRRR
0000000010100000
GR[reg2]
←
GR[reg2]arithmetically shift right
by GR[reg1]
1
1
1
×
0
×
×
SAR
imm5,reg2
r r r r r 0 1 0 1 0 1 i i i i i
GR[reg2]
←
GR[reg2]arithmetically shift right
by zero-extend (imm5)
1
1
1
×
0
×
×
SASF
cccc,reg2
rrrrr1111110cccc
0000001000000000
if conditions are satisfied
then GR[reg2]
←
(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]
←
(GR[reg2]Logically shift left by 1)
OR 00000000H
1
1
1
reg1,reg2
rrrrr000110RRRRR
GR[reg2]
←
saturated(GR[reg2]+GR[reg1])
1
1
1
×
×
×
×
×
SATADD
imm5,reg2
r r r r r 0 1 0 0 0 1 i i i i i
GR[reg2]
←
saturated(GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
×
SATSUB
reg1,reg2
rrrrr000101RRRRR
GR[reg2]
←
saturated(GR[reg2]–GR[reg1])
1
1
1
×
×
×
×
×
SATSUBI
imm16,reg1,reg2
rrrrr110011RRRRR
i i i i i i i i i i i i i i i i
GR[reg2]
←
saturated(GR[reg1]–sign-extend(imm16)
1
1
1
×
×
×
×
×
SATSUBR
reg1,reg2
rrrrr000100RRRRR
GR[reg2]
←
saturated(GR[reg1]–GR[reg2])
1
1
1
×
×
×
×
×
SETF
cccc,reg2
rrrrr1111110cccc
0000000000000000
If conditions are satisfied
then GR[reg2]
←
00000001H
else GR[reg2]
←
00000000H
1
1
1
bit#3,disp16[reg1]
00bbb111110RRRRR
dddddddddddddddd
adr
←
GR[reg1]+sign-extend(disp16)
Z flag
←
Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
3
Note 3
3
Note 3
3
Note 3
×
SET1
reg2,[reg1]
rrrrr111111RRRRR
0000000011100000
adr
←
GR[reg1]
Z flag
←
Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
3
Note 3
3
Note 3
3
Note 3
×