參數(shù)資料
型號(hào)： UPD703201
廠商： NEC Corp.
英文描述： 32-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 32位單晶片微控制器
文件頁數(shù)： 62/98頁
文件大小： 797K
代理商： UPD703201
Preliminary Product Information U15436EJ1V0PM
62
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(6/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
SXB
reg1
00000000101RRRRR
GR[reg1]
←
sign-extend
(GR[reg1] (7 : 0))
1
1
1
SXH
reg1
00000000111RRRRR
GR[reg1]
←
sign-extend
(GR[reg1] (15 : 0))
1
1
1
TRAP
vector
00000 1111 11iiiii
0000000100000000
EIPC
←
PC+4
(Restored PC)
←
PSW
EIPSW
ECR.EICC
←
Interrupt Code
PSW.EP
←
1
PSW.ID
←
1
PC
←
00000040H
(when vector is 00H to
0FH)
00000050H
(when vector is 10H to
1FH)
3
3
3
TST
reg1,reg2
rrrrr001011RRRRR
result
←
GR[reg2] AND GR[reg1]
1
1
1
0
×
×
bit#3,disp16[reg1]
11bbb111110RRRRR
dddddddddddddddd
adr
←
GR[reg1]+sign-extend(disp16)
Z flag
←
Not (Load-memory-bit (adr,bit#3))
3
Note 3
3
Note 3
3
Note 3
×
TST1
reg2, [reg1]
rrrrr111111RRRRR
0000000011100110
adr
←
GR[reg1]
Z flag
←
Not (Load-memory-bit (adr,reg2))
3
Note 3
3
Note 3
3
Note 3
×
XOR
reg1,reg2
rrrrr001001RRRRR
GR[reg2]
←
GR[reg2] XOR GR[reg1]
1
1
1
0
×
×
XORI
imm16,reg1,reg2
rrrrr110101RRRRR
i i i i i i i i i i i i i i i i
GR[reg2]
←
GR[reg1] XOR zero-extend (imm16)
1
1
1
0
×
×
ZXB
reg1
00000000100RRRRR
GR[reg1]
←
zero-extend (GR[reg1] (7 : 0))
1
1
1
ZXH
reg1
00000000110RRRRR
GR[reg1]
←
zero-extend (GR[reg1] (15 : 0))
1
1
1
Notes 1.
dddddddd: Higher 8 bits of disp9.
3 clocks if the final instruction includes the PSW write access.
If there is no wait state (3 + the number of read access wait states).
n is the total number of list X load registers. (According to the number of wait states. Also, if there are
no wait states, n is the number of list X registers.)
RRRRR: Other than 00000.
The lower halfword data only is valid.
ddddddddddddddddddddd: The higher 21 bits of disp22.
ddddddddddddddd: The higher 15 bits of disp16.
According to the number of wait states (1 if there are no wait states).
10.
b: Bit 0 of disp16.
11.
According to the number of wait states (2 if there are no wait states).
12.
In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
rrrrr
= regID specification
RRRRR = reg2 specification
13.
iiiii: Lower 5 bits of imm9.
IIII:
Lower 4 bits of imm9.
14.
sp/imm: Specified by bits 19 and 20 of the sub-opcode.
2.
3.
4.
5.
6.
7.
8.
9.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD703201GC-XXX-8EU 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703201Y 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703201YGC-XXX-8EU 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703204 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLERS
UPD703204F1-XXX-EA6 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT SINGLE-CHIP MICROCONTROLLERS
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