參數(shù)資料
型號: UPD703130
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 6/72頁
文件大?。?/td> 601K
代理商: UPD703130
Preliminary Data Sheet U15390EJ1V0DS
6
μ
PD703130
1. DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1
Product Name
V850E/MS2
V850E/MS1
Item
μ
PD703130
μ
PD703100-33
μ
PD703102-33
Internal ROM
None
None
128 KB (mask ROM)
Maximum
operating
frequency
33 MHz
33 MHz
Memory space
64 MB linear (only 22 MB supports on-chip
CS signal)
64 MB linear
Chip select output
4 spaces
8 spaces
Interrupt function
External: 10, internal: 35
External: 25, internal: 47
I/O lines
Input: 5, I/O: 52
Input: 9, I/O: 114
Timer
16-bit timer/event counter: 4 channels
16-bit timer: 2 channels
16-bit timer/event counter: 6 channels
16-bit timer: 2 channels
Serial interface
CSI/UART: 2 channels
Dedicated baud rate generator: 2 channels
CSI: 2 channels
CSI/UART: 2 channels
Dedicated baud rate generator: 3 channels
A/D converter
10-bit resolution
×
4 channels
10-bit resolution
×
8 channels
Package
100-pin plastic LQFP (fine-pitch) (14
×
14)
144-pin plastic LQFP (fine-pitch) (20
×
20)
Other
Noise tolerance and noise radiation will differ due to differences in circuit scale and mask layout.
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