參數(shù)資料
型號： UPD703130
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁數(shù)： 30/72頁
文件大小： 601K
代理商： UPD703130
Preliminary Data Sheet U15390EJ1V0DS
30
μ
PD703130
(d) DMA flyby transfer timing (SRAM
→
external I/O transfer) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT
↓
)
<24>
t
SWK
15
ns
WAIT hold time (from CLKOUT
↓
)
<25>
t
HKW
2
ns
RD low-level width
<32>
t
WRDL
(1 + w
D
+ w
F
+ w)
T
–
10
ns
RD high-level width
<33>
t
WRDH
T – 10
ns
Delay time from address, CSn to RD
↓
<34>
t
DARD
0.5T – 10
ns
Delay time from RD
↑
to address
<35>
t
DRDA
(0.5 + i)T – 10
ns
Delay time from RD
↑
to data output
<37>
t
DRDOD
(0.5 + i)T – 10
ns
WAIT setup time (to address)
<38>
t
SAW
Note
T – 25
ns
WAIT setup time (to BCYST
↓
)
<39>
t
SBSW
Note
T – 25
ns
WAIT hold time (from BCYST
↑
)
<40>
t
HBSW
Note
0
ns
Delay time from address to IOWR
↓
<41>
t
DAWR
0.5T – 10
ns
Address setup time (to IOWR
↑
)
<42>
t
SAWR
(1.5 + w
D
+ w)T – 10
ns
Delay time from IOWR
↑
to address
<43>
t
DWRA
0.5T – 10
ns
IOWR high-level width
<44>
t
WWRH
T – 10
ns
IOWR low-level width
<45>
t
WWRL
(1 + w
D
+ w)T – 10
ns
w
F
= 0
0
ns
Delay time from IOWR
↑
to RD
↑
<48>
t
DWRRD
w
F
= 1
T – 10
ns
Delay time from DMAAKm
↓
to IOWR
↓
<49>
t
DDAWR
0.5T – 10
ns
Delay time from IOWR
↑
to DMAAKm
↑
<50>
t
DWRDA
(0.5 + w
F
)T – 10
ns
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
T = t
CYK
2.
w: The number of waits due to WAIT.
3.
w
D
: The number of waits due to the DWC1 and DWC2 registers.
4.
w
F
: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
5.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
6.
n = 0, 3 to 5, m = 0 to 3
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