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參數(shù)資料
| 型號： | TTRN0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時鐘合成器，16:1數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時鐘合成器，16:1數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 633K |
| 代理商： | TTRN0110G |
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Advance Data Sheet
August 2000
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
7
Lucent Technologies Inc.
Pin Information
(continued)
Note:
In Table 2, when operating the TTRN0110G device at the OC-192/STM-64 rate, 10 Gbits/s should be
interpreted as 9.9532 Gbits/s. When operating the TTRN0110G device at the RS FEC OC-192/STM-64 rate,
10 Gbits/s should be interpreted as 10.6642 Gbits/s.
Table 2. Pin Descriptions—10 Gbits/s and Related Signals
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
indicates an internal pull-up resistor on this pin. I
d
indicates an internal pull-down resistor on this pin.
Pin
A11
A9
Symbol
*
D10GP
D10GN
Type
O
Level
CML
Name/Description
Data Output (10 Gbits/s NRZ).
10 Gbits/s differential data out-
put. Note that this data rate will scale by 15/14 when operating
at the FEC rate.
Loopback Data Output.
Additional 10 Gbits/s differential data
output for system loopback. Note that this data rate will scale by
15/14 when operating at the FEC rate.
Clock Output (10 GHz).
10 GHz differential clock output. Note
that this clock frequency will scale by 15/14 when operating at
the FEC rate.
FEC Rate (Active-Low).
Selects the normal OC-192/STM-64
rate of 9.9532 GHz or the FEC rate of 10.6642 GHz.
D1
F1
LBDP
LBDN
O
CML
A7
A5
CK10GP
CK10GN
O
CML
K14
FECN
I
u
CMOS
0 = FEC rate of 10.6642 GHz
1 or no connection = OC-192/STM-64 rate of 9.9532 GHz
Note that all input and output clock and data rates are scaled by
15/14 when operating at the FEC rate.
Resistor Reference CML.
CML current bias reference resistor.
(See Table 16, page 23 for values.)
Enable CK10GP/N Clock Output.
0 = CK10GP/N buffer powered off
1 or no connection = CK10GP/N buffer enabled
Enable LBDP/N Data Output (Active-Low).
0 = LBDP/N buffer enabled
1 or no connection = LBDP/N buffer powered off
Invert D10G Data Output (Active-Low).
0 = invert
1 or no connection = noninvert
Test Clock Input.
(Buffer is powered down when TESTN = 1.)
Select Test Clock (Active-Low).
0 = select test clock
1 or no connection = select VCO
Resistor Reference VCO.
VCO bias reference resistor.
Connect a
TBD
k
resistor to V
CCD
.
D8
RREFCML
I
Analog
F9
ENCK10G
I
u
CMOS
F7
ENLBDN
I
u
CMOS
E7
INVDATN
I
u
CMOS
C15
E9
TSTCKP
TESTN
I
CML
CMOS
I
u
F14
RREFVCO
I
Analog
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