參數(shù)資料
型號(hào)： TTRN0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器)
中文描述： 10 Gb /秒時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器）
文件頁數(shù)： 18/30頁
文件大?。?/td> 633K
代理商： TTRN0110G
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
Advance Data Sheet
August 2000
18
Lucent Technologies Inc.
CML Output Structure (Used on Pins D10GP/N, CK10GP/N, LBDP/N)
The CML architecture is essentially a current-steering mechanism combined with an amplifier. This makes the out-
put swing of the signal a function of the termination resistor and the output current. The on-chip, 50
termination
resistor provides a back termination and the output may be direct or ac-coupled to the load. For the direct coupled
case, the 50
load should be referenced to the positive 3.3 V supply, V
CC
. This will ensure dc levels that comply
with the limits set in Table 16 and Table 17 on page 23. The value for RREFCML is also given in these tables.
0358(F)
Figure 7. Typical CML Output Structure
–
+
INPUT SIGNAL
50
50
RREFCML
V
CC
IOUT
X
ENABLE
–
+
VREF
IREF
DEVICE-INTERNAL CML OUTPUT BUFFER CIRCUIT
50
50
C
C
EXTERNAL OUTPUT TERMINATION
IOUT
IOUT
50
50
V
TT
V
TT
NOTE: SHOWN FOR ac COUPLING;
DIRECT COUPLING MAY ALSO BE USED.
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