參數(shù)資料
型號(hào)： TTRN0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器)
中文描述： 10 Gb /秒時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器）
文件頁數(shù)： 17/30頁
文件大?。?/td> 633K
代理商： TTRN0110G
Advance Data Sheet
August 2000
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
17
Lucent Technologies Inc.
Clocking Modes and Timing Adjustments
(continued)
Clockless Transfer Mode (CLKMOD[1:0]= 11, EXTCNTR)
In clockless transfer mode (CLKMOD[1:0] = 11), data may be sent to the TTRN0110G device without providing
PICLKP/N. An internal delay-locked loop (DLL) automatically produces a 622 MHz clock that is aligned to the
parallel data based on the phase of the D0P/N data input. The skew of all data bits D[15:1]P/N relative to D0P/N
must be less than 650 ps as shown in Figure 11 on page 25.
An internal data buffer is used to absorb timing drift between D0 and the internal clocks derived from the 10 GHz
internal oscillator. A D0 phase drift of up to ±1600 ps relative to the internal clocks can be absorbed by the buffer,
as long as the bandwidth of this phase drift is less than 500 kHz. Note that the read and write addresses for the
data buffer must be initially reset in order for the buffer to absorb the full range of D[15:0]P/N phase drift.
The read and write addresses for the data buffer are reset at the time the PLL acquires lock and the loss of lock
indicator transitions from the out-of-lock condition to the in-lock condition. After LCKLOSSN goes high the buffer
will be centered and data integrity will be obtained within approximately 2
μ
s.
The data buffer can also be recentered by applying EXTCNTR (active high) for a minimum of 6.4 ns. After
EXTCNTR goes low the buffer will be centered and data integrity will be lost and subsequently restored within
approximately 2
μ
s.
If the timing drift exceeds ±1600 ps, the data buffer will indicate overflow with a logic-high signal on the OVRFLW
pin for a minimum of 6.4 ns. After a time interval of 4.8 ns after OVRFLW goes low the buffer will be recentered and
data integrity will be lost and subsequently restored within approximately 2
μ
s. During the 11.2 ns between the
rising edge of OVRFLW and the recentering of the buffer, data integrity may be lost if the timing drift exceeds
±2000 ps.
If the output clock CK622P/N is not used when in CLKMOD[1:0] = 11, it can be left unconnected to conserve
power.
Because the clockless data transfer mode uses the transitions on the D0 data bit as a phase reference for clocking
the data, a constraint of a maximum number of consecutive zeroes of less than
TBD
data periods is placed on the
D0 bit when operating in the clockless data transfer mode.
相關(guān)PDF資料
PDF描述
TUA-6034 3-Band Digital TV / Set-Top-Box Tuner IC TAIFUN
TUA6034-T MB 6C 6#20 SKT PLUG
TUA6034-V MB 10C 10#20 PIN PLUG
TUA6034 3-Band Digital TV / Set-Top-Box Tuner IC
TUA6036 3-Band Digital TV / Set-Top-Box Tuner IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TTRN012G5 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G53XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G7 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTRN012G73XE1 制造商:AGERE 制造商全稱:AGERE 功能描述:TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
TTR-RED 功能描述:打印機(jī) Ribbon, Resin, 4.33" W x 299’ L, for use RoHS:否 制造商:Seiko Instruments 產(chǎn)品:Printer 電源電壓: 每行點(diǎn)數(shù):9 x 320 打印速度:52.5 cps, 80 cps 紙張寬度:112 mm
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*