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參數(shù)資料
| 型號(hào)： | TTRN0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 21/30頁 |
| 文件大小： | 633K |
| 代理商： | TTRN0110G |
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Advance Data Sheet
August 2000
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
21
Lucent Technologies Inc.
Electrical Characteristics
(continued)
LVDS, CMOS, CML Output Pins
Notes:
1. For Table 12 through Table 19, V
CC
= 3.3 V ± 5%, Tambient = –40 °C to +85 °C.
2. For more information on interpreting CML specifications, see the CML Output Structure (Used on Pins
D10GP/N, CK10GP/N, LBDP/N) section on page 18.
Table 12. LVDS Output Pin Parametrics
* As defined in the IEEE
standard 1596.3 -1996.
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Applicable
Pins
CK622P/N,
CK155P/N
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Voh
Output Voltage High,
Voa or Vob
Output Voltage Low,
Voa or Vob
Output Differential Voltage
Output Offset Voltage
Differential Output
Impedance
Ro Mismatch Between
A & B
Change in |Vod| Between
Logic 0 and Logic 1
Change in |Vos| Between
Logic 0 and Logic 1
Output Current
Rload = 100
± 1%
—
—
1475
mV
Vol
Rload = 100
± 1%
925
—
—
mV
|Vod|
Vos
Ro
Rload = 100
± 1%
Rload = 100
± 1%
Vcm = 1.0 V and 1.4 V
250
1125
80
—
—
100
400
1275
280
mV
mV
Ro
Vcm = 1.0 V and 1.4 V
—
—
10
%
|
Vod|
Rload = 100
± 1%
—
—
25
mV
|
Vos|
Rload = 100
± 1%
—
—
25
mV
Isa, Isb
Driver shorted
to GND
Drivers shorted
together
—
—
—
24
mA
Isab
Output Current
—
—
12
mA
|Ixa|,|Ixb| Power-Off Output Leakage
Data Vod:
Rise Time, 20% to 80%
Fall Time, 20% to 80%
Clock Vod:
Rise Time, 20% to 80%
Fall Time, 20% to 80%
tskew1
Differential Skew*
tskew2
Channel to Channel*
—
—
TBD
mA
trised
tfalld
Zload = 100
± 1%
Zload = 100
± 1%
200
200
—
—
450
450
ps
ps
trisec
tfallc
Zload = 100
± 1%
Zload = 100
± 1%
—
—
100
100
—
—
—
—
—
—
450
450
TBD
200
ps
ps
ps
ps
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