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參數(shù)資料
| 型號： | TTRN0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時鐘合成器，16:1數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時鐘合成器，16:1數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 14/30頁 |
| 文件大小： | 633K |
| 代理商： | TTRN0110G |
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TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
Advance Data Sheet
August 2000
14
Lucent Technologies Inc.
Multiplexer Operation
The parallel 622 Mbits/s data is clocked into an input buffer then clocked into a 16:1 multiplexer. The relationship
between the parallel D[15:0]P/N input data and the serial output data D10GP/N is given in Figure 5. The D15 bit is
the most significant bit (MSB) and is shifted out first in time in the serial output stream.
5-8063(F)
Figure 5. Parallel Input to Serial Output Data Relationship
10 GHz Clock Output Enable (ENCK10G)
The 10 GHz clock output CK10GP/N may be disabled by setting the ENCK10G pin to logic low. ENCK10G is an
active-high CMOS input with a pull-up resistor so the default condition will enable the CK10GP/N output and a
ground or logic-low signal must be applied to disable the CK10GP/N output. When disabled, the CK10GP/N pins
should be either left floating or be connected to a load which returns to V
CC
. The output must not be connected
directly to ground when it is disabled.
Loopback 10 GHz Data Output (LBDP/N, ENLBDN)
An alternate 10 Gbits/s CML data output is available on the LBDP/N pin. This pin is provided for use in system
loopback testing and avoids the need for off-chip signal splitting of the data signal path. The alternate 10 Gbits/s
loopback data output may be enabled by setting the ENLBDN pin to logic low. ENLBDN enable is an active-low
CMOS input with a pull-up resistor so the default condition will disable the LBDP/N output, and a ground or logic-
low signal must be applied to enable the loopback output. When disabled, the LBDP/N pin should be either left
floating, or be connected to a load which returns to V
CC
. The output must not be connected directly to ground when
it is disabled.
Reset (RESETN)
The RESETN signal must be held active low for a minimum of 6.4 ns when the internal VCO is active and running,
in order for the internal logic to be completely reset.
D15
(MSB)
D14
D1
D0
(LSB)
D15
TIME
(D15 SERIALLY SHIFTED OUT FIRST)
(D0 SERIALLY SHIFTED OUT LAST)
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